Modelling and measurements of a composite microcantilever beam for chemical sensing applications

2006 ◽  
Vol 220 (10) ◽  
pp. 1601-1608 ◽  
Author(s):  
I R Voiculescu ◽  
M E Zaghloul ◽  
R A McGill ◽  
J F Vignola
Keyword(s):  
Resonant Frequency ◽  
Cantilever Beam ◽  
Gas Sensing ◽  
Laser Doppler Vibrometer ◽  
Beam Theory ◽  
Wheatstone Bridge ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Sensing Applications ◽  
Microcantilever Beam

A resonant microcantilever beam gas sensor was designed and fabricated in Carnegie Mellon University using complementary metal oxide semiconductor (CMU-CMOS) technology. The cantilever beam modified with a suitable sorbent coating was demonstrated as a chemical transducer for monitoring hazardous vapours and gases at trace concentrations. The design of the cantilever beam included interdigitated fingers to allow electrostatic actuation of the device and a piezoresistive Wheatstone bridge design to read out the deflection signal. The cantilever beam resonant frequency was modelled using the Euler-Bernoulli beam theory and ANSYS. The beam resonant frequency was measured with an optical laser Doppler vibrometer. Good agreement was obtained among the measured, simulated, and modelled resonant frequencies. A custom sorbent polymer layer was coated on the surface of the cantilever beam to allow its operation as a gas-sensing device. The frequency response as a function of exposure to the nerve agent simulant dimethylmethylphosphonate (DMMP) at different concentrations was measured, which allowed a demonstrated detection at a concentration of 20 ppb or 0.1 mg/m3. The air-polymer partition coefficient K, for DMMP was estimated and compared favourably with the known values for related polymers.

scholarly journals A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

2020 ◽  
Vol 10 (1) ◽  
pp. 399 ◽  
Author(s):  
Kwonsang Han ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Operational Amplifier ◽  
Wheatstone Bridge ◽  
Input Resistance ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Readout Integrated Circuit ◽  
Chopper Stabilization

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

scholarly journals A highly stable, nanotube-enhanced, CMOS-MEMS thermal emitter for mid-IR gas sensing

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Daniel Popa ◽  
Richard Hopper ◽  
Syed Zeeshan Ali ◽  
Matthew Thomas Cole ◽  
Ye Fan ◽  
...  
Keyword(s):  
Gas Sensing ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Mir Spectroscopy ◽  
Sensing Applications ◽  
Cmos Mems ◽  
Extended Operation ◽  
On Chip

AbstractThe gas sensor market is growing fast, driven by many socioeconomic and industrial factors. Mid-infrared (MIR) gas sensors offer excellent performance for an increasing number of sensing applications in healthcare, smart homes, and the automotive sector. Having access to low-cost, miniaturized, energy efficient light sources is of critical importance for the monolithic integration of MIR sensors. Here, we present an on-chip broadband thermal MIR source fabricated by combining a complementary metal oxide semiconductor (CMOS) micro-hotplate with a dielectric-encapsulated carbon nanotube (CNT) blackbody layer. The micro-hotplate was used during fabrication as a micro-reactor to facilitate high temperature (>700 $$^{\circ }$$ ∘ C) growth of the CNT layer and also for post-growth thermal annealing. We demonstrate, for the first time, stable extended operation in air of devices with a dielectric-encapsulated CNT layer at heater temperatures above 600 $$^{\circ }$$ ∘ C. The demonstrated devices exhibit almost unitary emissivity across the entire MIR spectrum, offering an ideal solution for low-cost, highly-integrated MIR spectroscopy for the Internet of Things.

scholarly journals A highly stable, nanotube-enhanced, CMOS-MEMS thermal emitter for mid-IR gas sensing

2021 ◽  
Author(s):  
Daniel Popa ◽  
Richard Hopper ◽  
Syed Zeeshan Ali ◽  
Matthew Cole ◽  
Ye Fan ◽  
...  
Keyword(s):  
Gas Sensing ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Light Sources ◽  
Mir Spectroscopy ◽  
Sensing Applications ◽  
Cmos Mems ◽  
Extended Operation ◽  
On Chip

Abstract The gas sensor market is growing fast, driven by many socioeconomic and industrial factors. Mid-infrared (MIR) gas sensors offer excellent performance for an increasing number of sensing applications in healthcare, smart homes, and the automotive sector. Having access to low-cost, miniaturized, energy efficient light sources is of critical importance for the monolithic integration of MIR sensors. Here, we present an on-chip broadband thermal MIR source fabricated by combining a complementary metal oxide semiconductor (CMOS) micro-hotplate with a dielectric-encapsulated carbon nanotube (CNT) blackbody layer. The micro-hotplate was used during fabrication as a micro-reactor to facilitate high temperature (>700 • C) growth of the CNT layer and also for post-growth thermal annealing. We demonstrate, for the first time, stable extended operation in air of devices with a dielectric-encapsulated CNT layer at heater temperatures above 600 • C. The demonstrated devices exhibit almost unitary emissivity across the entire MIR spectrum, offering an ideal solution for low-cost, highly-integrated MIR spectroscopy for the Internet of Sensors.

Introduction of a Novel Sample Preparation Technique for the Failure Analysis of Silicon Integrated Photonics Modules

2019 ◽  
Author(s):  
Pradip Sairam Pichumani ◽  
Fauzia Khatkhatay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Silicon Photonics ◽  
Cmos Technology ◽  
Single Step ◽  
Oxide Semiconductor ◽  
Disruptive Technology ◽  
Preparation Technique ◽  
Test Vehicle ◽  
Sample Preparation Technique

Abstract Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

Effect of Grain Size on Strain in a Copper Oxide Nanofilm for Gas Sensing Applications

2019 ◽  
Vol 11 (5) ◽  
pp. 05040-1-05040-4
Author(s):  
Sumanta Kumar Tripathy ◽  
◽  
Sanjay Kumar ◽  
Divya Aparna Narava ◽  
◽  
...  
Keyword(s):  
Grain Size ◽  
Copper Oxide ◽  
Gas Sensing ◽  
Sensing Applications

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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