scholarly journals High Gain, Two-Stage, Fully Differential Audio Amplifier with 0.18μm CMOS Technology

2014 ◽  
Vol 2 (1) ◽  
pp. 6-10
Author(s):  
Siavash Heydarzadeh ◽  
Ramezan Ali Sadeghzadeh
Keyword(s):  
Cmos Technology ◽  
High Gain ◽  
Two Stage ◽  
Fully Differential ◽  
Audio Amplifier

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals A Sub-mW 18-MHz MEMS Oscillator Based on a 98-dBΩ Adjustable Bandwidth Transimpedance Amplifier and a Lamé-Mode Resonator

Sensors ◽  
2019 ◽  
Vol 19 (12) ◽  
pp. 2680
Author(s):  
Anoir Bouchami ◽  
Mohannad Y. Elsayed ◽  
Frederic Nabki
Keyword(s):  
Phase Noise ◽  
Cmos Technology ◽  
High Gain ◽  
Transimpedance Amplifier ◽  
Short Term ◽  
Microelectromechanical System ◽  
Fully Differential ◽  
Mems Oscillator ◽  
Measured Input ◽  
Mode Resonator

This paper presents a microelectromechanical system (MEMS)-based oscillator based on a Lamé-mode capacitive micromachined resonator and a fully differential high-gain transimpedance amplifier (TIA). The proposed TIA is designed using TSMC 65 nm CMOS technology and consumes only 0.9 mA from a 1-V supply. The measured mid-band transimpedance gain is 98 dB Ω and the TIA features an adjustable bandwidth with a maximum bandwidth of 142 MHz for a parasitic capacitance C P of 4 pF. The measured input-referred current noise of the TIA at mid-band is below 15 pA/ Hz . The TIA is connected to a Lamé-mode resonator, and the oscillator performance in terms of phase noise and frequency stability is presented. The measured phase noise under vacuum is −120 dBc/Hz at a 1-kHz offset, while the phase noise floor reaches −127 dBc/Hz. The measured short-term stability of the MEMS-based oscillator is ±0.25 ppm.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

scholarly journals Design of Low Power, High Gain Fully Differential Folded Cascode Operational Amplifier for Front End Read Out Circuits

2019 ◽  
Vol 8 (4) ◽  
pp. 1802-1808
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Operational Amplifier ◽  
Cmos Technology ◽  
High Gain ◽  
Vital Role ◽  
Open Loop ◽  
Fully Differential ◽  
Front End ◽  
Folded Cascode

The Front end read out circuits are major block in the implementation of Capacitive MEMS accelerometer. Front end read-out circuits comprises of preamplifier block containing folded cascode fully differential operational amplifier which are required for the signal conditioning of the signals received from the MEMS sensors. The op-amps are prime elements in design and implementation of mixed signal integrated circuits. The high gain and low power of the designed circuits helps in the designing of high precision IC’s for numerous application. Amongst the available topologies folded cascode topology plays vital role in the design and development of low power, high gain read out circuits. This paper illustrates the design and analysis of low power, high gain fully differential Folded Cascode Operational Amplifier for front end read out circuits. The designed op-amp exhibits a power consumption or dissipation of 92.14 μW and relatively higher open loop DC gain value with a value calculated at 81.33 dB by employing folded cascode topology. The UGB and Phase Margin for the selected design are 35 MHz and 83.60 respectively. The design operates at 5V power supply with the bias current of 12.11 μA. The circuit design and simulations have been implemented using 0.18 μm CMOS technology.

scholarly journals Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 188
Author(s):  
Žiga Korošak ◽  
Nejc Suhadolnik ◽  
Anton Pleteršek
Keyword(s):  
Radio Frequency Identification ◽  
High Efficiency ◽  
Near Field ◽  
Cmos Technology ◽  
Near Field Communication ◽  
Differential Delay ◽  
Fully Differential ◽  
Delay Locked Loop ◽  
Modulation Wave ◽  
The Individual

The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high-efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation components. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360° delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and maximum power consumption under 7.5 mW.

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