Low-Power Electro-Optic Actuators for Large-Scale Programmable Photonic Circuits

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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Performance Analysis of Routing Protocol for Low Power and Lossy Networks (RPL) in Large Scale Networks

IEEE Internet of Things Journal ◽

10.1109/jiot.2017.2755980 ◽

2017 ◽

Vol 4 (6) ◽

pp. 2172-2185 ◽

Cited By ~ 28

Author(s):

Xiyuan Liu ◽

Zhengguo Sheng ◽

Changchuan Yin ◽

Falah Ali ◽

Daniel Roggen

Keyword(s):

Performance Analysis ◽

Low Power ◽

Routing Protocol ◽

Large Scale ◽

Lossy Networks ◽

Large Scale Networks

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A Resonator-based Silicon Electro-optic Modulator with Ultra-low Power Consumption and Optimized Modulation Performance

2008 IEEE PhotonicsGlobal@Singapore ◽

10.1109/ipgc.2008.4781305 ◽

2008 ◽

Author(s):

Maoqing Xin ◽

Aaron J. Danner ◽

Ching Eng Png ◽

Soon Thor Lim

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Ultra Low Power ◽

Electro Optic ◽

Electro Optic Modulator

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Temperature distribution of SiC bed surface in a large-scale microwave-assisted pyrolysis reactor

10.22541/au.161507416.69287974/v1 ◽

2021 ◽

Author(s):

Ying Duan ◽

Xiaogen Yi ◽

Qinglong Xie ◽

Zhengai Weng ◽

Peng Yuan ◽

...

Keyword(s):

Temperature Distribution ◽

Low Power ◽

Large Scale ◽

Scale Up ◽

Microwave Pyrolysis ◽

Microwave Assisted ◽

Stable Temperature ◽

Microwave Reactors ◽

Pyrolysis Reactor ◽

Scale Reactor

Microwave reactors equipped with microwave absorbent as high-temperature bed are effective for the pyrolysis reactions. The uniformity and stability of temperature distribution on the microwave absorbent bed surface is important to the microwave pyrolysis reactor especially in the large-scale reactor. Herein, the temperature distribution on the SiC microwave absorbent bed in a large-scale microwave pyrolysis reactor without feeding was examined by both infrared thermography and simulation. Considering the economics of using multiple low-power magnetrons in large-scale reactor, the effect of the working magnetrons location on the heating rate of bed surface and the COV of temperature distribution was investigated. The results showed that more uniform and stable temperature distribution of bed surface in the large-scale reactor was obtained when the magnetrons located at the bottom of the reactor were in use. This study provides guidance for the scale-up of microwave-assisted pyrolysis reactor with multiple low-power magnetrons.

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Coupling of waveguide mode and graphene plasmons

EPJ Web of Conferences ◽

10.1051/epjconf/202125507002 ◽

2021 ◽

Vol 255 ◽

pp. 07002

Author(s):

Jiří Petráček ◽

Jiří Čtyroký ◽

Vladimír Kuzmiak ◽

Pavel Kwiecien ◽

Ivan Richter

Keyword(s):

Low Power ◽

Graphene Layer ◽

Waveguide Mode ◽

Chemical Potential ◽

Temperature Sensing ◽

Graphene Layers ◽

Optical Wavelength ◽

Electro Optic ◽

Photonic Waveguides ◽

Graphene Plasmons

Photonic waveguides with graphene layers have been recently studied for their potential as fast and low-power electro-optic modulators with small footprints. We show that in the optical wavelength range of 1.55 μm, surface plasmons supported by the graphene layer with the chemical potential exceeding ~0.5 eV can couple with the waveguide mode and affect its propagation. This effect might be possibly utilized in technical applications as a very low-power amplitude modulation, temperature sensing, etc.

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Reversible logic in pipelined low power vedic multiplier

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v16.i3.pp1265-1272 ◽

2019 ◽

Vol 16 (3) ◽

pp. 1265

Author(s):

Ansiya Eshack ◽

S. Krishnakumar

Keyword(s):

Low Power ◽

Communication Systems ◽

Large Scale ◽

Optical Computing ◽

Digital Signal ◽

Logic Gates ◽

Reversible Logic ◽

Large Scale Integration ◽

Time Required ◽

Scale Integration

<span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span>

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ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis

Neural Computation ◽

10.1162/neco_a_01107 ◽

2018 ◽

Vol 30 (9) ◽

pp. 2472-2499 ◽

Cited By ~ 2

Author(s):

Zhitong Qiao ◽

Yan Han ◽

Xiaoxia Han ◽

Han Xu ◽

Will X. Y. Li ◽

...

Keyword(s):

Low Power ◽

Integrated Circuit ◽

Large Scale ◽

Random Number Generator ◽

Core Area ◽

Dynamical Model ◽

Volterra Model ◽

Nonlinear Dynamical ◽

The Core ◽

Nonlinear Dynamical Model

A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)–generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm[Formula: see text] and test power of 84.4 [Formula: see text]W. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.

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