scholarly journals Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes

2016 ◽  
Vol 16 (5) ◽  
pp. 260-265 ◽  
Author(s):  
David Matoušek ◽  
Jiří Hospodka ◽  
Ondřej Šubrt
Keyword(s):  
Output Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Specific Power ◽  
Pump Efficiency ◽  
Clock Frequency ◽  
Output Current ◽  
Charge Pumps ◽  
Complex Optimization ◽  
Charge Pump Circuit

Abstract Charge pumps are circuits that produce the voltage higher than supply voltage or negative voltage. Today, charge pumps became an integral part of the electronic equipment. The integration of charge pumps directly into the system allows manufacturers to feed a complex system with many specific power requirements from a single source. However, charge pump efficiency is reduced by many phenomena. This paper is focused on the question of efficiency of proposed variant of the charge pump. In this article, the efficiency dependence on a number of stages, output current, clock frequency and MOSFETs sizes was simulated by Eldo. The aim of this study is to determine the MOSFETs sizes and theirs influence to efficiency and the output voltage. Complex optimization of the charge pump circuit will follow in further text.

scholarly journals New Discrete Fibonacci Charge Pump Design, Evaluation and Measurement

2017 ◽  
Vol 17 (3) ◽  
pp. 100-107 ◽  
Author(s):  
David Matoušek ◽  
Jiří Hospodka ◽  
Ondřej Šubrt
Keyword(s):  
Printed Circuit Board ◽  
Charge Pump ◽  
Circuit Board ◽  
Design Evaluation ◽  
Clock Frequency ◽  
Pump Design ◽  
Charge Pumps ◽  
Printed Circuit ◽  
Variable Power ◽  
Charge Pump Circuit

AbstractThis paper focuses on the practical aspects of the realisation of Dickson and Fibonacci charge pumps. Standard Dickson charge pump circuit solution and new Fibonacci charge pump implementation are compared. Both charge pumps were designed and then evaluated by LTspice XVII simulations and realised in a discrete form on printed circuit board (PCB). Finally, the key parameters as the output voltage, efficiency, rise time, variable power supply and clock frequency effects were measured.

High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique

2015 ◽  
Vol 764-765 ◽  
pp. 506-510
Author(s):  
Yung Chin Chen
Keyword(s):  
Threshold Voltage ◽  
Output Voltage ◽  
Voltage Drop ◽  
Charge Pump ◽  
Pump Efficiency ◽  
Dc Voltage ◽  
Pumping Efficiency ◽  
High Efficient ◽  
Efficient Charge ◽  
Charge Pump Circuit

This paper proposed an improved bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump in order to get a higher pumping efficiency. It is not only avoid the threshold voltage drop in conventional Dickson charge pump circuits but enable them to generate a higher output voltage. Simulation by HSPICE shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.76 times of it (VOUT=7.14V), the pump efficiency can reaches as high as 95.2%.

scholarly journals A 5 V to 180 V Charge Pump for Capacitive Loads in a 180 nm SOI Process

2021 ◽  
Author(s):  
Jakob K. Toft ◽  
Ivan H. H. Jorgensen
Keyword(s):  
High Voltage ◽  
Rise Time ◽  
Output Voltage ◽  
Supply Voltage ◽  
State Of The Art ◽  
Charge Pump ◽  
Micro Electro Mechanical System ◽  
Charge Pumps ◽  
Capacitive Load ◽  
Very High

This paper presents two variants of a high step-up ratio charge pump for high voltage micro electro-mechanical system and condenser microphones. The implementations are based on an additive charge pump topology where respectively 46 and 57 cascaded stages are used to generate an output voltage of 182 V from a supply voltage of 5 V. The two charge pumps have been fabricated in a 180 nm SOI process with a breakdown voltage of more than 200 V and respectively occupy an area of 0.52 mm2 and 0.39 mm2. The charge pumps can output up to 182.5 V and 181.7 V and are designed to drive a capacitive load with a leakage of 2 nA. When driven with a 100 kHz clock, their power consumption is respectively 40 µW and 20 µW. The rise time of the charge pumps output from 0 V to 182 V is less than 5 ms. The implemented charge pumps exhibit state-of-the-art performance for very high voltage dc-dc capacitive drive applications.

scholarly journals Review a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power

2018 ◽  
Vol 7 (3.1) ◽  
pp. 27
Author(s):  
Vengadeswari N ◽  
Priscilla Whitin
Keyword(s):  
Supply Voltage ◽  
Charge Pump ◽  
Major Elements ◽  
Leakage Power ◽  
Power Gating ◽  
Charge Pumps ◽  
Pumping Efficiency ◽  
Low Power Cmos ◽  
Two Parameters ◽  
Charge Pump Circuit

In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools. 

scholarly journals Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

2018 ◽  
Vol 8 (6) ◽  
pp. 4120
Author(s):  
Sung Sik Park ◽  
Ju Sang Lee ◽  
Sang Dae Yu
Keyword(s):  
Circuit Simulation ◽  
Pulse Height ◽  
Charge Pump ◽  
Cmos Process ◽  
Charge Pumps ◽  
Current Matching ◽  
Low Jitter ◽  
A New Technique ◽  
Charge Pump Circuit ◽  
Frequency Detector

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

DESIGN OF MODIFIED FOUR-PHASE CMOS CHARGE PUMPS FOR LOW-VOLTAGE FLASH MEMORIES

2002 ◽  
Vol 11 (04) ◽  
pp. 393-403 ◽  
Author(s):  
HONGCHIN LIN ◽  
NAI-HSIEN CHEN ◽  
JAINHAO LU
Keyword(s):  
Power Efficiency ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Flash Memories ◽  
Clock Generation ◽  
Charge Pumps ◽  
Main Charge

A new four-phase clock scheme for the four-phase charge pumping circuits using standard 0.5 μm CMOS technology at low supply voltages to generated high boosted voltages is proposed. Boosted clocks without high drivability are applied on the capacitors coupled to the gates of the main charge transfer transistors to compensate body effects. Thus, the high-voltage clock generation circuit can be easily achieved for clock frequency of 10 MHz. Due to the nearly ideal pumping gain per stage, the design methodology to optimize power efficiency is also presented. With the new clock scheme, it can efficiently pump to 9 V at supply voltage of 1 V using 10 stages by simulations, while pump to 4.7 V at supply voltage of 1.5 V using four stages by measurements.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

2019 ◽  
Vol 29 (01) ◽  
pp. 2050013
Author(s):  
Najmeh Cheraghi Shirazi ◽  
Abumoslem Jannesari ◽  
Pooya Torkzadeh
Keyword(s):  
Power Consumption ◽  
Transient Response ◽  
Output Voltage ◽  
Low Voltage ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Voltage Ripple ◽  
Body Biasing

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

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