Characterization of Reduced-pressure Chemical Vapor Deposition Polycrystalline Silicon Germanium Deposited at Temperatures ≤550 °C

2002 ◽  
Vol 17 (7) ◽  
pp. 1580-1586 ◽  
Author(s):  
Sherif Sedky ◽  
Ann Witvrouw ◽  
Matty Caymax ◽  
Annelies Saerens ◽  
Paul Van Houtte
Keyword(s):  
Silicon Germanium ◽  
Deposition Temperature ◽  
Polycrystalline Silicon ◽  
Chemical Vapor ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Reduced Pressure ◽  
Germanium Content ◽  
Wafer Temperature ◽  
The Impact

This paper investigates the possibility of reducing the deposition temperature of polycrystalline silicon germanium to a level compatible with complementary metal-oxide semiconductor (CMOS) post processing. To achieve this goal, the exact wafer temperature during deposition was experimentally determined and it was found to be 30 °C lower than the reactor setting temperature. The deposition temperature was reduced from 625 to 500 °C. The impact of varying the deposition pressure from 10 to 760 torr and the germanium content from 15% to 100% was investigated. X-ray diffraction spectroscopy and transmission electron microscopy showed that the SixGe1−x films deposited at an actual wafer temperature of 520 °C are polycrystalline for germanium contents as low as 15%. Also, it was shown that the deposition conditions can be adjusted to yield a low tensile stress at an actual wafer temperature of 520 °C, which is suitable for integrating surface micromachined micro-electromechanical systems on top of standard CMOS wafers with Al interconnects.

Rapid Thermal Chemical Vapor Deposition of Polycrystalline Silicon-Germanium Films on SiO2 and Their Properties

1995 ◽  
Vol 403 ◽  
Author(s):  
V. Z-Q Li ◽  
M. R. Mirabedini ◽  
R. T. Kuehn ◽  
D. Gladden ◽  
D. Batchelor ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Silicon Germanium ◽  
Deposition Temperature ◽  
Chemical Vapor ◽  
Grain Structure ◽  
Germanium Content ◽  
Thermal Chemical Vapor Deposition ◽  
Nucleation Sites

AbstractIn this work, polycrystalline SiGe has been viewed as an alternative gate material to polysilicon in single wafer processing for the deep submicrometer VLSI applications. We studied deposition of the silicon-germanium (SiGe) films with different germanium concentrations (up to 85%) on SiO2 in a rapid thermal chemical vapor deposition reactor using GeH4 and SiH4/H2 gas mixture with the temperature ranging from 550°C to 625°C. Since the SiGe RTCVD process is selective toward oxide and does not form nucleation sites on the oxide easily, an in-situ polysilicon flash technique is used to provide the necessary nucleation sites for the deposition of SiGe films with high germanium content. It was observed that with the in-situ polysilicon flash as a pre-nucleation seed, the SiGe deposited on SiO2 forms a continuous polycrystalline layer. Polycrystalline SiGe films of about 2000Å in thickness have a columnar grain structure with a grain size of approximately 1000Å. Compositional analyses from Auger Electron Spectroscopy (AES) and Rutherford backscattering (RBS) show that the high germanium incorporation in the SiGe films has a weak dependence on the deposition temperature. It is also noted that the germanium content across the film thickness is fairly constant which is a critical factor for the application of SiGe films as the gate material. Lastly, we found that the surface morphology of SiGe films become smoother at lower deposition temperature.

Effect of in situ boron doping on properties of silicon germanium films deposited by chemical vapor deposition at 400 °C

2001 ◽  
Vol 16 (9) ◽  
pp. 2607-2612 ◽  
Author(s):  
Sherif Sedky ◽  
Ann Witvrouw ◽  
Annelies Saerens ◽  
Paul Van Houtte ◽  
Jef Poortmans ◽  
...  
Keyword(s):  
Silicon Germanium ◽  
Boron Concentration ◽  
Microelectromechanical Systems ◽  
Chemical Vapor ◽  
Oxide Semiconductor ◽  
Germanium Content ◽  
Seeding Layer ◽  
Glass Substrates ◽  
Transmission Electron

This paper reports on the role of boron in situ doping on enhancing crystallization of silicon germanium deposited at 400 °C and 2 torr. The dependence of growth rate on germanium content and boron concentration is investigated. The minimum boron concentration and the minimum germanium content required for crystallizing the as-grown layers is experimentally determined. The texture and grain microstructure of doped and undoped poly SiGe layers has been investigated by means of x-ray diffraction spectroscopy and transmission electron microscopy. The low deposition temperature coupled with the low tensile stress of the polycrystalline material enable postprocessing of surface micromachined microelectromechanical systems on top of standard complementry metal oxide semiconductor wafers with Al interconnects. Furthermore, the resistivity of the as-grown layers is as low as 1 mΩ cm, and hence, it can be used as a seeding layer for polycrystalline Si solar cells compatible with glass substrates.

The Effect of Temperature and Pressure on Residual Stress in LPCVD Polysilicon Films

1992 ◽  
Vol 276 ◽  
Author(s):  
D-G. Oei ◽  
S. L. McCarthy
Keyword(s):  
Residual Stress ◽  
Deposition Temperature ◽  
Polycrystalline Silicon ◽  
Chemical Vapor ◽  
Effect Of Temperature ◽  
Pressure Chemical ◽  
Polysilicon Films ◽  
Oriented Polycrystalline ◽  
Temperature And Pressure ◽  
Reduced Pressures

ABSTRACTMeasurements of the residual stress in polysilicon films made by Low Pressure Chemical Vapor Deposition (LPCVD) at different deposition pressures and temperatures are reported. The stress behavior of phosphorus (P)-ion implanted/annealed polysilicon films is also reported. Within the temperature range of deposition, 580 °C to 650 °C, the stress vs deposition temperature plot exhibits a transition region in which the stress of the film changes from highly compressive to highly tensile and back to highly compressive as the deposition temperature increases. This behavior was observed in films that were made by the LPCVD process at reduced pressures of 210 and 320 mTORR. At deposition temperatures below 590 °C the deposit is predominantly amorphous, and the film is highly compressive; at temperatures above 610 °C (110) oriented polycrystalline silicon is formed exhibiting high compressive residual stress.

scholarly journals A New Approach to the Fabrication of Memristive Neuromorphic Devices: Compositionally Graded Films

Materials ◽  
2020 ◽  
Vol 13 (17) ◽  
pp. 3680
Author(s):  
Jong-Gul Yoon
Keyword(s):  
Short Term Memory ◽  
Chemical Vapor ◽  
Complementary Metal Oxide Semiconductor ◽  
Information Storage ◽  
Oxide Semiconductor ◽  
Film Electrode ◽  
Retention Performance ◽  
Short Term ◽  
Neuromorphic Computing ◽  
Term Memory

Energy-efficient computing paradigms beyond conventional von-Neumann architecture, such as neuromorphic computing, require novel devices that enable information storage at nanoscale in an analogue way and in-memory computing. Memristive devices with long-/short-term synaptic plasticity are expected to provide a more capable neuromorphic system compared to traditional Si-based complementary metal-oxide-semiconductor circuits. Here, compositionally graded oxide films of Al-doped MgxZn1−xO (g-Al:MgZnO) are studied to fabricate a memristive device, in which the composition of the film changes continuously through the film thickness. Compositional grading in the films should give rise to asymmetry of Schottky barrier heights at the film-electrode interfaces. The g-Al:MgZnO films are grown by using aerosol-assisted chemical vapor deposition. The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the films show self-rectifying memristive behaviors which are dependent on maximum applied voltage and repeated application of electrical pulses. Endurance and retention performance tests of the device show stable bipolar resistance switching (BRS) with a short-term memory effect. The short-term memory effects are ascribed to the thermally activated release of the trapped electrons near/at the g-Al:MgZnO film-electrode interface of the device. The volatile resistive switching can be used as a potential selector device in a crossbar memory array and a short-term synapse in neuromorphic computing.

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

2007 ◽  
Vol 46 (1) ◽  
pp. 51-55 ◽  
Author(s):  
Genshiro Kawachi ◽  
Yoshiaki Nakazaki ◽  
Hiroyuki Ogawa ◽  
Masayuki Jyumonji ◽  
Noritaka Akita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Circuits

Analysis of Logic Inverter Based on Polycrystalline Silicon with Single Grain Boundary

2020 ◽  
Vol 20 (11) ◽  
pp. 6616-6621
Author(s):  
Hye Jin Mun ◽  
Min Su Cho ◽  
Jun Hyeok Jung ◽  
Won Douk Jang ◽  
Sang Ho Lee ◽  
...  
Keyword(s):  
Grain Boundary ◽  
Polycrystalline Silicon ◽  
Complementary Metal Oxide Semiconductor ◽  
Deep Trap ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Shallow Trap ◽  
Nanoscale Cmos ◽  
Dc Characteristics ◽  
Single Grain

In this paper, we demonstrate the characteristics of a complementary metal-oxide-semiconductor (CMOS) logic inverter based on a polycrystalline-silicon (poly-Si) layer with a single grain boundary (GB). The proposed nanoscale CMOS logic inverter had been constructed on a poly-Si layer with a GB including four kind of traps at the center of the channel. The simulation variables are the acceptor-like deep trap (ADT), the donor-like deep trap (DDT), the acceptor-like shallow trap (AST) and the donor-like shallow trap (DST). The ADT and the DDT much stronger influences on the DC characteristics of the devices than the AST and the DST. The variation of voltage-transfer-curve (VTC) for CMOS devices directly affected the CMOS logic inverter with different traps.

The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor

2009 ◽  
Vol 48 (1) ◽  
pp. 011208
Author(s):  
Eiji Morifuji ◽  
Hideki Kimijima ◽  
Kenji Kojima ◽  
Masaaki Iwai ◽  
Fumitomo Matsuoka
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Impact Of Technology ◽  
The Impact

Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon

2006 ◽  
Vol 910 ◽  
Author(s):  
Czang-Ho Lee ◽  
Andrei Sazonov ◽  
Mohammad R. E. Rad ◽  
G. Reza Chaji ◽  
Arokia Nathan
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Chemical Vapor ◽  
Hole Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Nanocrystalline Silicon ◽  
Oxide Semiconductor ◽  
Hole Injection ◽  
Current Ratio

AbstractWe report on directly deposited plasma-enhanced chemical vapor deposition (PECVD) nanocrystalline silicon (nc-Si:H) ambipolar thin-film transistors (TFTs) fabricated at 260 °C. The ambipolar operation is achieved adopting Cr metal contacts with high-quality nc-Si:H channel layer, which creates highly conductive Cr silicided drain/source contacts, reducing both electron and hole injection barriers. The n-channel nc-Si:H TFTs show a field-effect electron mobility (meFE) of 150 cm2/Vs, threshold voltage (VT) ~ 2 V, subthreshold slope (S) ~0.3 V/dec, and ON/OFF current ratio of more than 107, while the p-channel nc-Si:H TFTs show a field-effect hole mobility (mhFE) of 26 cm2/Vs, VT ~ -3.8 V, S ~0.25 V/dec, and ON/OFF current ratio of more than 106. Complementary metal-oxide-semiconductor (CMOS) logic integrated with two ambipolar nc-Si:H TFTs shows reasonable transfer characteristics. The results presented here demonstrate that low-temperature nc-Si:H TFT technology is feasible for total integration of active-matrix TFT backplanes.

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