Alternative method of interface traps passivation by introducing of thin silicon nitride layer at 4H-SiC/SiO2 interface

2014 ◽  
Vol 1693 ◽  
Author(s):  
Aleksey I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
Victor V. Luchinin ◽  
Sergey A. Reshanov ◽  
Adolf Schöner
Keyword(s):  
Silicon Nitride ◽  
Silicon Oxide ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Nitride Layer ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Devices ◽  
Inversion Channel ◽  
P Type

ABSTRACTAn alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

Passivation of 4H-SiC/SiO2 Interface Traps by Oxidation of a Thin Silicon Nitride Layer

2015 ◽  
Vol 821-823 ◽  
pp. 508-511 ◽  
Author(s):  
A.I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
Victor V. Luchinin ◽  
S.A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Gate Oxide ◽  
Nitride Layer ◽  
Interface Roughness ◽  
Field Effect Mobility ◽  
Mos Devices ◽  
Nitridation Process ◽  
Silicon Nitride Layer ◽  
Inversion Channel ◽  
Thin Silicon

The effect of the alternative nitridation process of the 4H-SiC/SiO2interface by introduction of a thin silicon nitride layer on the electrical properties of the gate oxide has been investigated.C-VandG-Vmeasurements on inversion-channel MOS devices revealed similar results to the conventional N2O oxidation. Higher field-effect mobility values are achieved due to lower interface roughness of the alternative nitridation process. However, insignificant degradation of the reliability was observed.

Sodium Enhanced Oxidation of Si-Face 4H-SiC: A Method to Remove Near Interface Traps

2007 ◽  
Vol 556-557 ◽  
pp. 487-492 ◽  
Author(s):  
Einar Ö. Sveinbjörnsson ◽  
Fredrik Allerstam ◽  
H.Ö. Ólafsson ◽  
G. Gudjónsson ◽  
D. Dochev ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Energy Levels ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Interface Traps ◽  
Channel Mobility ◽  
Inversion Channel ◽  
Enhanced Oxidation

We demonstrate how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2/4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1-10 cm2/Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these nearinterface traps resulting in high inversion channel mobility of 150 cm2/Vs in such transistors. Sodium can be incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during formation of the SiC/SiO2 interface.

Impact of Ge Content on Flicker Noise Behavior of Strained-SiGe p-Type Metal–Oxide–Semiconductor Field-Effect Transistors

2009 ◽  
Vol 48 (4) ◽  
pp. 04C036 ◽  
Author(s):  
San-Lein Wu ◽  
Chung Yi Wu ◽  
Hau-Yu Lin ◽  
Cheng-Wen Kuo ◽  
Shin-Hsin Chen ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Flicker Noise ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
P Type ◽  
Strained Sige

scholarly journals Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Energies ◽  
2019 ◽  
Vol 12 (12) ◽  
pp. 2310 ◽  
Author(s):  
Patrick Fiorenza ◽  
Filippo Giannazzo ◽  
Fabrizio Roccaforte
Keyword(s):  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Chemical Characterization ◽  
Oxide Semiconductor ◽  
Physical Parameters ◽  
Characterization Methods ◽  
Channel Mobility ◽  
Doping Effects ◽  
Transient Capacitance ◽  
Microscopy Techniques

This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

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