3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces

2008 ◽  
Vol 1112 ◽  
Author(s):  
Jian-Qiang Lu ◽  
J. Jay McMahon ◽  
Ronald J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Emerging Technology ◽  
3D Integration ◽  
Multiple Materials ◽  
Similarities And Differences ◽  
Functional Components

AbstractThree-dimensional (3D) integration is an emerging technology that vertically stacks and interconnects multiple materials, technologies and functional components to form highly integrated micro/nano-systems. This paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces. Similarities and differences in architectural advantages and technology challenges are presented, with recent research advances discussed.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Three Dimensional Integration with Benzocyclobutene as the Wafer-Bonding Medium

2004 ◽  
Vol 833 ◽  
Author(s):  
Sang Kevin Kim ◽  
Lei Xue ◽  
Sandip Tiwari
Keyword(s):  
Integrated Circuits ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Experimental Results ◽  
Device Layer ◽  
3D Integration ◽  
Wafer Scale ◽  
3D Ics ◽  
Fabrication Procedure ◽  
3D Fabrication

ABSTRACTA successful wafer-scale device layering process for fabricating three-dimensional integrated circuits (3D ICs) using Benzocyclobutene (BCB) is described. In the reported embodiment of the method, a sub-micron thick “donor” device layer is transplanted onto a fully fabricated “host” wafer with BCB as the intervening medium. Experimental results, including RIE study and planarization of BCB processed through the 3D fabrication procedure are reported. We conclude with an approach to alleviate BCB and fabrication induced wafer bowing, which leads to poor wafer to wafer alignment in 3D integration.

Wafer Bonding Using Dielectric Polymer Thin Films in 3D Integration

2001 ◽  
Vol 710 ◽  
Author(s):  
Y. Kwon ◽  
J.-Q. Lu ◽  
R. P. Kraft ◽  
J. F. McDonald ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Stability ◽  
Wafer Bonding ◽  
Polymer Thin Films ◽  
Three Dimensional ◽  
Bonding Process ◽  
3D Integration ◽  
Razor Blade ◽  
Chemical Structures ◽  
Dielectric Polymer

ABSTRACTA key process in our approach to monolithic three-dimensional (3D) integration is the bonding of 200-mm wafers using dielectric polymer thin films as bonding glues. After discussing the desired properties of polymer thin films, we describe how bonding protocols are evaluated using silicon and glass wafers. After bonding, the fraction of bonded area was inspected optically and a razor blade method was used to indicate bonding strength. Thermal stability and bonding integrity were evaluated using thermal cycling and backside grinding and polishing. To date, we have studied benzocyclobutene (BCB), Flare™, and methylsilsesquioxane (MSSQ) and Parylene-N as bonding glues. Wafer pairs bonded using BCB showed a larger fraction of bonded area, and those using Flare indicated higher thermal stability. Both BCB and Flare glues provided good bonding integrity after backside grinding tests. Changes in the chemical structures of BCB and Flare glue during bonding were analyzed using FTIR in order to understand the bonding mechanism and to improve the bonding process.

Low-Temperature PETEOS-to-PETEOS Wafer Bonding Using Titanium as Bonding Intermediate

2006 ◽  
Vol 914 ◽  
Author(s):  
Jian Yu ◽  
Richard L. Moore ◽  
Sang Hwui Lee ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Low Temperature ◽  
Wafer Bonding ◽  
Electron Spectroscopy ◽  
Auger Electron ◽  
Three Dimensional ◽  
3D Integration ◽  
Patterned Wafers ◽  
Scanning Electron

AbstractBonding of pre-processed silicon wafers at back-end-of-the-line (BEOL) compatible conditions is one of the attractive approaches for three-dimensional (3D) integration. Among various technologies being evaluated, bonding of low temperature oxides (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)) is of great interest. In this work, we report low-temperature PETEOS-to-PETEOS wafer bonding, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength is evaluated qualitatively, while the bonding interface is examined by Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Preliminary results of PETEOS/Ti/PETEOS bonding on patterned wafers with single-level Cu damascene structures are also discussed.

(ECS Meeting PRiME 2020) High TEC copper to connect copper bond pads for low temperature wafer bonding

2020 ◽  
Author(s):  
Anh Van Nhat Tran ◽  
Kazuo Kondo ◽  
Tetsuji Hirato
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Three Dimensional ◽  
Copper Surface ◽  
Bonding Process ◽  
3D Integration ◽  
High Thermal Expansion ◽  
Lower Temperature ◽  
Bond Pads ◽  
High Thermal Expansion Coefficient

Copper to copper wafer hybrid bonding is the most promising technology for three-dimensional (3D) integration. In the hybrid bonding process, two silicon wafers are aligned and contacted. At room temperature, these aligned copper pads contain radial-shaped nanometer-sized hollows due to the dishing effect induced by chemical-mechanical polishing (CMP). These wafers are annealed for copper to expand and connect upper and lower pads. This copper expansion is key to eliminate the radial-shaped hollows and make copper pads contacted. Therefore, in this research, we investigated the new high thermal expansion coefficient (TEC) electrodeposited copper to eliminate dishing hollows at lower temperature than that with conventional copper using the combination of new additive A and three other additives. The TEC of new electrodeposited copper is 25.2 x 10-6 oC-1, 46% higher than conventional copper and the calculated contact area of copper surface at 250oC with 5 nm dishing depth is 100%.

scholarly journals Three-dimensional(3D) printing in forensic science–An emerging technology in India

2021 ◽  
Vol 1 ◽  
pp. 100006
Author(s):  
Gargi Jani ◽  
Abraham Johnson ◽  
Jeidson Marques ◽  
Ademir Franco
Keyword(s):  
3D Printing ◽  
Forensic Science ◽  
Three Dimensional ◽  
Emerging Technology

Decomposition of Event-Related Brain Potentials into Multiple Functional Components Using Wavelet Transform

2001 ◽  
Vol 32 (3) ◽  
pp. 122-138 ◽  
Author(s):  
Tamer Demiralp ◽  
Ahmet Ademoglu
Keyword(s):  
Wavelet Transform ◽  
Three Dimensional ◽  
Experimental Session ◽  
Brain Potentials ◽  
Time Frequency ◽  
Similar Characterization ◽  
Component Identification ◽  
Frequency Components ◽  
Neurophysiological Mechanisms ◽  
Functional Components

Event related brain potential (ERP) waveforms consist of several components extending in time, frequency and topographical space. Therefore, an efficient processing of data which involves the time, frequency and space features of the signal, may facilitate understanding the plausible connections among the functions, the anatomical structures and neurophysiological mechanisms of the brain. Wavelet transform (WT) is a powerful signal processing tool for extracting the ERP components occurring at different time and frequency spots. A technical explanation of WT in ERP processing and its four distinct applications are presented here. The first two applications aim to identify and localize the functional oddball ERP components in terms of certain wavelet coefficients in delta, theta and alpha bands in a topographical recording. The third application performs a similar characterization that involves a three stimulus paradigm. The fourth application is a single sweep ERP processing to detect the P300 in single trials. The last case is an extension of ERP component identification by combining the WT with a source localization technique. The aim is to localize the time-frequency components in three dimensional brain structure instead of the scalp surface. The time-frequency analysis using WT helps isolate and describe sequential and/or overlapping functional processes during ERP generation, and provides a possibility for studying these cognitive processes and following their dynamics in single trials during an experimental session.

Unraveling the Mystery of Brazilian Jeitinho

2011 ◽  
Vol 38 (3) ◽  
pp. 331-344 ◽  
Author(s):  
Maria Cristina Ferreira ◽  
Ronald Fischer ◽  
Juliana Barreiros Porto ◽  
Ronaldo Pilati ◽  
Taciano L. Milfont
Keyword(s):  
Social Norm ◽  
Three Dimensional ◽  
Social Dominance Orientation ◽  
Dimensional Structure ◽  
Social Psychological ◽  
Indigenous Psychology ◽  
The Social ◽  
Problem Solving Strategies ◽  
Functional Components ◽  
Scenario Approach

Two studies explore the structure and psychological makeup of jeitinho, a Brazilian indigenous construct associated with problem-solving strategies in strong hierarchies. Study 1 used a scenario approach with nonstudent participants and demonstrated that jeitinho can be described by a three-dimensional structure: corruption, creativity, and social norm breaking. Study 2 used individual and social norm scenarios in nonstudent samples and demonstrated that moral leniency is associated with more corruption and social norm breaking. Furthermore, only in the personal but not the social norm condition was greater social dominance orientation associated with more corruption and social norm breaking. Jeitinho is not a monolitical construct, but it is a complex sociocultural strategy that has distinct functional components at the personal and normative levels. Theoretical advances in the understanding of social norms and indigenous psychology by examining both culture-specific and general social-psychological processes are outlined.

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