(ECS Meeting PRiME 2020) High TEC copper to connect copper bond pads for low temperature wafer bonding

2020 ◽  
Author(s):  
Anh Van Nhat Tran ◽  
Kazuo Kondo ◽  
Tetsuji Hirato
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Three Dimensional ◽  
Copper Surface ◽  
Bonding Process ◽  
3D Integration ◽  
High Thermal Expansion ◽  
Lower Temperature ◽  
Bond Pads ◽  
High Thermal Expansion Coefficient

Copper to copper wafer hybrid bonding is the most promising technology for three-dimensional (3D) integration. In the hybrid bonding process, two silicon wafers are aligned and contacted. At room temperature, these aligned copper pads contain radial-shaped nanometer-sized hollows due to the dishing effect induced by chemical-mechanical polishing (CMP). These wafers are annealed for copper to expand and connect upper and lower pads. This copper expansion is key to eliminate the radial-shaped hollows and make copper pads contacted. Therefore, in this research, we investigated the new high thermal expansion coefficient (TEC) electrodeposited copper to eliminate dishing hollows at lower temperature than that with conventional copper using the combination of new additive A and three other additives. The TEC of new electrodeposited copper is 25.2 x 10-6 oC-1, 46% higher than conventional copper and the calculated contact area of copper surface at 250oC with 5 nm dishing depth is 100%.

Wafer Bonding Using Dielectric Polymer Thin Films in 3D Integration

2001 ◽  
Vol 710 ◽  
Author(s):  
Y. Kwon ◽  
J.-Q. Lu ◽  
R. P. Kraft ◽  
J. F. McDonald ◽  
R.J. Gutmann ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Stability ◽  
Wafer Bonding ◽  
Polymer Thin Films ◽  
Three Dimensional ◽  
Bonding Process ◽  
3D Integration ◽  
Razor Blade ◽  
Chemical Structures ◽  
Dielectric Polymer

ABSTRACTA key process in our approach to monolithic three-dimensional (3D) integration is the bonding of 200-mm wafers using dielectric polymer thin films as bonding glues. After discussing the desired properties of polymer thin films, we describe how bonding protocols are evaluated using silicon and glass wafers. After bonding, the fraction of bonded area was inspected optically and a razor blade method was used to indicate bonding strength. Thermal stability and bonding integrity were evaluated using thermal cycling and backside grinding and polishing. To date, we have studied benzocyclobutene (BCB), Flare™, and methylsilsesquioxane (MSSQ) and Parylene-N as bonding glues. Wafer pairs bonded using BCB showed a larger fraction of bonded area, and those using Flare indicated higher thermal stability. Both BCB and Flare glues provided good bonding integrity after backside grinding tests. Changes in the chemical structures of BCB and Flare glue during bonding were analyzed using FTIR in order to understand the bonding mechanism and to improve the bonding process.

3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces

2008 ◽  
Vol 1112 ◽  
Author(s):  
Jian-Qiang Lu ◽  
J. Jay McMahon ◽  
Ronald J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Emerging Technology ◽  
3D Integration ◽  
Multiple Materials ◽  
Similarities And Differences ◽  
Functional Components

AbstractThree-dimensional (3D) integration is an emerging technology that vertically stacks and interconnects multiple materials, technologies and functional components to form highly integrated micro/nano-systems. This paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces. Similarities and differences in architectural advantages and technology challenges are presented, with recent research advances discussed.

Integrated GaAs Diode Technology for Millimeter and Submillimeter-wave Components and Systems

2000 ◽  
Vol 631 ◽  
Author(s):  
Thomas W. Crowe ◽  
Jeffrey L. Hesler ◽  
William L. Bishop ◽  
Willie E. Bowen ◽  
Richard F. Bradley ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Flip Chip ◽  
Quartz Substrate ◽  
Submillimeter Wave ◽  
Bonding Process ◽  
Circuit Performance ◽  
Embedding Impedance ◽  
Compact Range ◽  
The Cost

ABSTRACTGaAs Schottky barrier diodes remain a workhorse technology for submillimeter-wave applications including radio astronomy, chemical spectroscopy, atmospheric studies, plasma diagnostics and compact range radar. This is because of the inherent speed of these devices and their ability to operate at room temperature. Although planar (flip-chip and beam-lead) diodes are replacing whisker contacted diodes throughout this frequency range, the handling and placement of such small GaAs chips limits performance and greatly increases component costs. Through the use of a novel wafer bonding process we have fabricated and tested submillimeter-wave components where the GaAs diode is integrated on a quartz substrate along with other circuit elements such as filters, probes and bias lines. This not only eliminates the cost of handling microscopically small chips, but also improves circuit performance. This is because the parasitic capacitance is reduced by the elimination of the GaAs substrate and the electrical embedding impedance seen by the diodes is more precisely controlled. Our wafer bonding process has been demonstrated through the fabrication and testing of a fundamental mixer at 585 GHz (Tmix < 1200K) and a 380 GHz subharmonically pumped mixer (Tmix < 1000K). This paper reviews the wafer bonding process and discusses how it can be used to greatly improve the performance and manufacturability of submillimeter-wave components.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Three Dimensional Integration with Benzocyclobutene as the Wafer-Bonding Medium

2004 ◽  
Vol 833 ◽  
Author(s):  
Sang Kevin Kim ◽  
Lei Xue ◽  
Sandip Tiwari
Keyword(s):  
Integrated Circuits ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Experimental Results ◽  
Device Layer ◽  
3D Integration ◽  
Wafer Scale ◽  
3D Ics ◽  
Fabrication Procedure ◽  
3D Fabrication

ABSTRACTA successful wafer-scale device layering process for fabricating three-dimensional integrated circuits (3D ICs) using Benzocyclobutene (BCB) is described. In the reported embodiment of the method, a sub-micron thick “donor” device layer is transplanted onto a fully fabricated “host” wafer with BCB as the intervening medium. Experimental results, including RIE study and planarization of BCB processed through the 3D fabrication procedure are reported. We conclude with an approach to alleviate BCB and fabrication induced wafer bowing, which leads to poor wafer to wafer alignment in 3D integration.

An Optimized 300mm BCB Wafer Bonding Process for 3D Integration

2010 ◽  
Vol 1249 ◽  
Author(s):  
Pratibha Singh ◽  
John Hudnall ◽  
Jamal Qureshi ◽  
Vimal Kumar Kamineni ◽  
Chris Taylor ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Bonding Process ◽  
Acoustic Microscopy ◽  
Cross Linking ◽  
Process Conditions ◽  
Optimization Approach ◽  
3D Integration ◽  
Razor Blade ◽  
Integration Schemes ◽  
The Impact

AbstractWafer bonding using benzocyclobutene (BCB) has been discussed in the past for three-dimensional (3D) integration. This paper reports the development and characterization of a manufacturable BCB bonding process for 300 mm wafers using standard 300 mm tools. A systematic optimization approach has been developed to characterize the bulk properties of the BCB film that can be applied to various integration schemes. We specifically discuss one such application—handle wafer bonding. BCB bonding for a range of cross-linking levels has been investigated. The cross-linking level of BCB before bonding is determined using an infrared (IR) variable angle spectroscopic ellipsometer (VASE) technique. The impact of the BCB film preparation and bonding condition on bond quality is characterized using scanning acoustic microscopy (SAM) , IR microscopy, a razor blade test, and four-point bend methods. Based on the results, an optimum cross-linking level for BCB film before bonding was determined for 300 mm wafers to obtain void-free and dendrite-free bonds. Wafers bonded using the optimized BCB process conditions have successfully sustained backgrinding, dry thinning, and standard BEOL metallization steps.

Low-Temperature PETEOS-to-PETEOS Wafer Bonding Using Titanium as Bonding Intermediate

2006 ◽  
Vol 914 ◽  
Author(s):  
Jian Yu ◽  
Richard L. Moore ◽  
Sang Hwui Lee ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Low Temperature ◽  
Wafer Bonding ◽  
Electron Spectroscopy ◽  
Auger Electron ◽  
Three Dimensional ◽  
3D Integration ◽  
Patterned Wafers ◽  
Scanning Electron

AbstractBonding of pre-processed silicon wafers at back-end-of-the-line (BEOL) compatible conditions is one of the attractive approaches for three-dimensional (3D) integration. Among various technologies being evaluated, bonding of low temperature oxides (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)) is of great interest. In this work, we report low-temperature PETEOS-to-PETEOS wafer bonding, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength is evaluated qualitatively, while the bonding interface is examined by Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Preliminary results of PETEOS/Ti/PETEOS bonding on patterned wafers with single-level Cu damascene structures are also discussed.

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

2020 ◽  
Vol 142 (3) ◽  
Author(s):  
Leila Choobineh ◽  
Robert Carrol ◽  
Carlos Gutierrez ◽  
Robert Geer
Keyword(s):  
Temperature Distribution ◽  
Field Programmable Gate Array ◽  
Thermal Modeling ◽  
Three Dimensional ◽  
Test Structure ◽  
Integration Process ◽  
3D Integration ◽  
Field Programmable ◽  
Gate Array ◽  
Bond Pads

Abstract This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

ZoneBOND Thin Wafer Support Process for Wafer Bonding Applications

2010 ◽  
Vol 7 (3) ◽  
pp. 138-142 ◽  
Author(s):  
Jeremy McCutcheon ◽  
Robert Brown ◽  
JoElle Dachsteiner
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Bonding Process ◽  
Temporary Bonding ◽  
Higher Temperature

The ZoneBOND process has been developed as an alternative temporary bonding process that bonds at an acceptable temperature (usually less than 200°C), survives through higher-temperature processes, and then debonds at room temperature. The technology utilizes standard silicon or glass carriers and current thermoplastic adhesives developed by Brewer Science, Inc.

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