Submicron P-Channel Mos Devices with Boron Doped Polysilicon Gates Fabricated by Rapid Thermal Processing

1990 ◽  
Vol 182 ◽  
Author(s):  
Sheldon M. Kugelmass ◽  
J. Peter Krusius

AbstractA low thermal budget process is demonstrated for the fabrication of submicron Boron doped polysilicon gate p-channel MOS devices with ultra thin gate insulators. All critical processing steps with temperatures above 700 °C, including gate oxide growth and shallow source/drain junction formation, were performed by Rapid Thermal Processing (RTP). In situ doped polysilicon was used to eliminate the need for a high temperature drive-in step. Surface channel p-channel enhancement mode devices with excellent characteristics were fabricated to demonstrate the feasibility of this process.

1996 ◽  
Vol 429 ◽  
Author(s):  
Binh Nguyenphu ◽  
Minseok Oh ◽  
Anthony T. Fiory

AbstractCurrent trends of silicon integrated circuit manufacturing demand better temperature control in various thermal processing steps. Rapid thermal processing (RTP) has become a key technique because its single wafer process can accommodate the reduced thermal budget requirements arising from shrinking the dimensions of devices and the trend to larger wafers. However, temperature control by conventional infrared pyrometry, which is highly dependent on wafer back side conditions, is insufficiently accurate for upcoming technologies. Lucent Technologies Inc., formerly known as AT&T Microelectronics and AT&T Bell Laboratories, has developed a powerful real-time pyrometry technique using the A/C ripple signal from heating lamps for in-situ temperature measurement. Temperature and electrical data from device wafers have been passively collected by ripple pyrometers in three RTP systems and analyzed. In this paper we report the statistical analysis of ripple temperature and electrical data from device wafers for a typical implant anneal process temperature range of 900 to 1000 °C.


1994 ◽  
Vol 21 (2) ◽  
pp. 137-141 ◽  
Author(s):  
Mahesh K. Sanganeria ◽  
Katherine E. Violette ◽  
Mehmet C. Öztürk ◽  
Gari Harris ◽  
C.Archie Lee ◽  
...  

2016 ◽  
Vol 67 (3) ◽  
pp. 231-233 ◽  
Author(s):  
Barbora Mojrová

Abstract This article deals with the investigation of the influence of sintering conditions on the formation process of screen printed contacts on passivated boron doped P+ emitters. The experiment was focused on measuring of resistance changes of two thick film pastes during firing processes with different conditions. Two different temperature profiles were compared at an atmospheric concentration of O2. The influence of the O2 concentration on resistance was investigated for one profile. A rapid thermal processing furnace modified for in-situ resistance measurements was used. The change of resistance was measured simultaneously with the temperature.


1998 ◽  
Vol 525 ◽  
Author(s):  
M. R. Mirabedini ◽  
V. Z-Q Li ◽  
A. R. Acker ◽  
R. T. Kuehn ◽  
D. Venables ◽  
...  

ABSTRACTIn this work, in-situ doped polysilicon and poly-SiGe films have been used as the gate material for the fabrication of MOS devices to evaluate their respective performances. These films were deposited in an RTCVD system using a Si2H6 and GeH4 gas mixture. MOS capacitors with 45 Å thick gate oxides and polysilicon/poly-SiGe gates were subjected to different anneals to study boron penetration. SIMS analysis and flat band voltage measurements showed much lower boron penetration for devices with poly-SiGe gates than for devices with polysilicon gates. In addition, C-V measurements showed no poly depletion effects for poly-SiGe gates while polysilicon gates had a depletion effect of about 8%. A comparison of resistivities of these films showed a low resistivity of 1 mΩ-cm for poly-SiGe films versus 3 mΩ-cm for polysilicon films after an anneal at 950 °C for 30 seconds.


1997 ◽  
Vol 70 (13) ◽  
pp. 1700-1702 ◽  
Author(s):  
R. Singh ◽  
K. C. Cherukuri ◽  
L. Vedula ◽  
A. Rohatgi ◽  
S. Narayanan

1998 ◽  
Vol 525 ◽  
Author(s):  
John R. Hauser

ABSTRACTScaling of MOS devices is projected to continue down to device dimensions of at least 50 nm. However, there are many potential roadblocks to achieving such dimensions and many standard materials and front-end processes which must be significantly changed to achieve these goals. The most important areas for change include (a) gate dielectric materials, (b) gate contact material, (c) source/drain contacting structure and (d) fundamental bulk CMOS structure. These projected changes are reviewed along with possible applications of rapid thermal processing to achieving future nanometer scale MOS devices.


1989 ◽  
Vol 146 ◽  
Author(s):  
Fred Ruddell ◽  
Colin Parkes ◽  
B Mervyn Armstrong ◽  
Harold S Gamble

ABSTRACTThis paper describes a LPCVD reactor which was developed for multiple sequential in-situ processing. The system is capable of rapid thermal processing in the presence of plasma stimulation and has been used for native oxide removal, plasma oxidation and silicon deposition. Polysilicon layers produced by the system are incorporated into N-P-N polysilicon emitter bipolar transistors. These devices fabricated using a sequential in-situ plasma clean-polysilicon deposition schedule exhibited uniform gains limited to that of long single crystal emitters. Devices with either plasma grown or native oxide layers below the polysilicon exhibited much higher gains. The suitability of the system for sequential and limited reaction processing has been established.


1994 ◽  
Vol 33 (Part 1, No. 12B) ◽  
pp. 7061-7070 ◽  
Author(s):  
Gerald Lucovsky ◽  
Yi Ma ◽  
Sunil V. Hattangady ◽  
David R. Lee ◽  
Zhong Lu ◽  
...  

2015 ◽  
Vol 86 (1) ◽  
pp. 013902 ◽  
Author(s):  
Md. Imteyaz Ahmad ◽  
Douglas G. Van Campen ◽  
Jeremy D. Fields ◽  
Jiafan Yu ◽  
Vanessa L. Pool ◽  
...  

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