Study of Transport Through Low-Temperature GaAs Surface Insulator Layers

1991 ◽  
Vol 241 ◽  
Author(s):  
J. P. Ibbetson ◽  
L.-W. Yin ◽  
M. Hashemi ◽  
A. C. Gossard ◽  
U. K. Mishra
Keyword(s):  
Material Properties ◽  
Surface Effect ◽  
Thin Layers ◽  
Gate Insulator ◽  
High Resistivity ◽  
Growth Surface ◽  
Insulator Layer ◽  
Insulator Layers ◽  
Low Temperature Gaas ◽  
Effective Buffer

ABSTRACTSince epilayers of GaAs grown at low substrate temperature (LTGaAs) and annealed at 600°C were first demonstrated to be an effective buffer layer for eliminating backgating effects, the material properties and electronic characteristics of bulk LTGaAs have been actively investigated. Less attention has been paid to thin layers of LTGaAs (∼2000Å), although these have been shown to improve gate-to-drain breakdown characteristics when incorporated as the surface insulator layer in GaAs MISFET's. In bulk LTGaAs that has been annealed for 10 minutes at 600°C, the formation of arsenic precipitates with a density of 1018 cm-3 has been observed. These are considered to be at least partially responsible for the high resistivity of LTGaAs2. While the exact mechanism of precipitate formation is currently unknown, it would seem reasonable to expect the availability of the growth surface to have a significant effect on any defect redistribution during the anneal. This surface effect would become increasingly apparent as the LTGaAs layer thickness was decreased. It is desirable for MISFET applications that the LTGaAs gate insulator layer be as thin as possible, whilst maintaining high breakdown, in order to maximize device transconductance. To achieve this, it is important to understand how the observed bulk features (such as ∼60Å size arsenic precipitates) are affected in thin LTGaAs layers

scholarly journals Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
P. T. Tue ◽  
T. Miyasako ◽  
E. Tokumitsu ◽  
T. Shimoda
Keyword(s):  
Thin Film ◽  
Indium Tin Oxide ◽  
Thin Film Transistor ◽  
Charge Injection ◽  
Memory Window ◽  
Gate Insulator ◽  
Insulator Layer ◽  
Capping Layer ◽  
Insulator Layers ◽  
Injection Effect

We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT) which uses solution-processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator.

Study of Modulation in GaAs Misfets with LT-GaAs as a Gate Insulator

1991 ◽  
Vol 241 ◽  
Author(s):  
L.-W. Yin ◽  
J. Ibbetson ◽  
M. M. Hashemi ◽  
W. Jiang ◽  
S.-Y. Hu ◽  
...  
Keyword(s):  
Low Temperature ◽  
Gaas Layer ◽  
Gate Insulator ◽  
Gate Bias ◽  
Channel Current ◽  
Turn On ◽  
Dc Characteristics ◽  
Low Temperature Gaas ◽  
Channel Separation ◽  
Lt Gaas

ABSTRACTDC characteristics of a GaAs MISFET structure using low-temperature GaAs (LTGaAs) as the gate insulator were investigated. MISFETs with different gate to channel separation (d) were fabricated. The dependence of four important device parameters such as gate-drain breakdown voltage (VBR), channel current at zero gate bias (Idss), transconductance (gm), and gate-drain turn-on voltage (Von) on the gate insulator thickness were analyzed. It was observed that (a) in terms of Idss and gin, the LT-GaAs gate insulator behaves like an undoped regular GaAs layer and (b) in terms of VBR and Von, the LT-GaAs gate insulator behaves as a trap dominated layer.

Recessed-Gate GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistor Using a Dual Gate-Insulator Employing TiO2/SiN

2020 ◽  
Vol 20 (8) ◽  
pp. 4678-4683
Author(s):  
Jun Hyeok Jung ◽  
Min Su Cho ◽  
Won Douk Jang ◽  
Sang Ho Lee ◽  
Jaewon Jang ◽  
...  
Keyword(s):  
Electron Mobility ◽  
High Electron Mobility Transistor ◽  
Gate Insulator ◽  
High Electron ◽  
Insulator Layer ◽  
Metal Insulator ◽  
High Electron Mobility ◽  
Metal Insulator Semiconductor ◽  
Dual Gate ◽  
Recessed Gate

In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO2/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO2/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO2 gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO2 gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.3 V, a maximum drain current of 556 mA/mm, a low Ron, sp of 1.45 mΩ·cm2, and a breakdown voltage of 631 V at an off-state current of 1 μA/mm with VGS = 0 V. We have confirmed that a normally-off recessed-gate AlGaN/GaN MIS-HEMT using a TiO2/SiN dual gate-insulator is a promising candidate for power electronic applications.

High resistivity annealed low-temperature GaAs with 100 fs lifetimes

2003 ◽  
Vol 83 (20) ◽  
pp. 4199-4201 ◽  
Author(s):  
I. S. Gregory ◽  
C. Baker ◽  
W. R. Tribe ◽  
M. J. Evans ◽  
H. E. Beere ◽  
...  
Keyword(s):  
Low Temperature ◽  
High Resistivity ◽  
Low Temperature Gaas

Triple-probe Atomic Force Microscope: Measuring a carbon nanotube/DNA MIS-FET

2002 ◽  
Vol 761 ◽  
Author(s):  
Kei Shimotani ◽  
Hiroyuki Watanabe ◽  
Chikara Manabe ◽  
Taishi Shigematsu ◽  
Masaaki Shimizu
Keyword(s):  
Carbon Nanotube ◽  
Atomic Force Microscope ◽  
Gate Insulator ◽  
Switching Behavior ◽  
Insulator Layer ◽  
Terminal Device ◽  
Atomic Force ◽  
Current Voltage ◽  
Dna Strands ◽  
Walled Carbon Nanotubes

ABSTRACTWe have constructed an advanced electric probing system, which is a triple-probe atomic force microscope (T-AFM). The T-AFM consists of “Nanotweezers” and an AFM with a carbon nanotube probe. Using this system, we fabricated a single-walled carbon nanotubes (SWNTs)/deoxyribonucleic acid (DNA) three-terminal device and measured the current-voltage (I-V) curves of this device. In this three-terminal device, DNA strands were entangled with the SWNT bundle, and behaved as a gate-insulator-layer. This three-terminal device worked as a metal-insulator-semiconductor field effect transistor (MIS-FET) with depletion switching behavior.

Hybrid Analytical and Experimental Method for Characterization of Thin Multilayer Bonded Structures Subject to Thermal Loading

2018 ◽  
Author(s):  
Alireza Shirazi ◽  
Hua Lu ◽  
Ahmad Varvani
Keyword(s):  
Thermal Cycling ◽  
Material Properties ◽  
Accurate Determination ◽  
High Accuracy ◽  
Thin Layers ◽  
Material Behavior ◽  
Interfacial Stress ◽  
Bonding Layer ◽  
Global Deformation ◽  
Warpage Deformation

This study is presenting a non-local closed-form solution for interfacial stress/strain and the warpage deformation for thin trilayer plate structures under thermal cycling. Based on the theory of geometric scale dependency of the material behavior, the material properties of a thin multi-layer inter-bonded structures substantially differ from those determined based on the bulk material samples. Hence the real mechanical properties for such thin layers are often unavailable and difficult to obtain. This paper puts forward a method to provide a solution for thermomechanical behavior of trilayer constituents with high accuracy at real scale. Present study demonstrates that the constitutive behavior of multilayer plate’s constituents can be inversely determined so long as the plate’s global deformation can be made available by measurement. To achieve most accurate determination of the material properties, measurements with high accuracy is required. The paper also presents the advanced method of shadow moiré that have applied to obtain warpage deformation of real life trilayer test specimens under thermal cycling. Using this method, the experimentally determined global deformation (warpage) of a trilayer structure were correlated with the analytical model solved for warpage deformation. The correlation was then progressively optimized to result in material properties of the constituents. The bonding layer properties are called determined, once the correlation reaches over 85%. There exist a variety of different multilayer bonded structures, which are usually made with advanced manufacturing processes. Regardless of design layout and materials constitutive relations, the application can be implemented in characterizing multiply stacked trilayer structures.

Triple-probe Atomic Force Microscope: Measuring a carbon nanotube/DNA MIS-FET

2002 ◽  
Vol 738 ◽  
Author(s):  
Kei Shimotani ◽  
Hiroyuki Watanabe ◽  
Chikara Manabe ◽  
Taishi Shigematsu ◽  
Masaaki Shimizu
Keyword(s):  
Carbon Nanotube ◽  
Atomic Force Microscope ◽  
Gate Insulator ◽  
Switching Behavior ◽  
Insulator Layer ◽  
Terminal Device ◽  
Atomic Force ◽  
Current Voltage ◽  
Dna Strands ◽  
Walled Carbon Nanotubes

ABSTRACTWe have constructed an advanced electric probing system, which is a triple-probe atomic force microscope (T-AFM). The T-AFM consists of “Nanotweezers” and an AFM with a carbon nanotube probe. Using this system, we fabricated a single-walled carbon nanotubes (SWNTs)/deoxyribonucleic acid (DNA) three-terminal device and measured the current-voltage (I-V) curves of this device. In this three-terminal device, DNA strands were entangled with the SWNT bundle, and behaved as a gate-insulator-layer. This three-terminal device worked as a metal-insulator-semiconductor field effect transistor (MIS-FET) with depletion switching behavior.

Impurity Effects in the Growth of 4H-SiC Crystals by Physical Vapor Transport

1999 ◽  
Vol 572 ◽  
Author(s):  
V. Balakrishna ◽  
G. Augustine ◽  
R. H. Hopkins
Keyword(s):  
Electronic Device ◽  
Defect Density ◽  
Growth Parameters ◽  
Large Diameter ◽  
Growth Conditions ◽  
High Resistivity ◽  
Growth Surface ◽  
Second Phase ◽  
Impurity Effects ◽  
Growth Environment

ABSTRACTSiC is an important wide bandgap semiconductor material for high temperature and high power electronic device applications. Purity improvements in the growth environment has resulted in a two-fold benefit during growth: (a) minimized inconsistencies in the background doping resulting in high resistivity (>5000 ohm-cm) wafer yield increase from 10–15% to 70-85%, and (b) decrease in micropipe formation. Growth parameters play an important role in determining the perfection and properties of the SiC crystals, and are extremely critical in the growth of large diameter crystals. Several aspects of growth are vital in obtaining highly perfect, large diameter crystals, such as: (i) optimized furnace design, (ii) high purity growth environment, and (iii) carefully controlled growth conditions. Although significant reduction in micropipe density has been achieved by improvements in the growth process, more stringent device requirements mandate further reduction in the defect density. In-depth understanding of the mechanisms of micropipe formation is essential in order to devise approaches to eliminate them. Experiments have been performed to understand the role of growth conditions and ambient purity on crystal perfection by intentionally introducing arrays of impurity sites on one half of the growth surface. Results clearly suggest that presence of impurities or second phase inclusions during start or during growth can result in the nucleation of micropipes. Insights obtained from these studies were instrumental in the growth of ultra-low micropipe density (less than 2 micropipes cm−2 ) in 1.5 inch diameter boules.

Material Properties Controlling the Performance of Amorphous Silicon Thin Film Transistors

1984 ◽  
Vol 33 ◽  
Author(s):  
M. J. Powell
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Amorphous Silicon ◽  
Density Of States ◽  
Threshold Voltage ◽  
Material Properties ◽  
Thin Film Transistors ◽  
Gate Insulator ◽  
Dangling Bond ◽  
Silicon Thin Film

ABSTRACTAmorphous silicon thin film transistors have been fabricated with a number of different structures and materials. To date, the best performance is obtained with amorphous silicon - silicon nitride thin film transistors in the inverted staggered electrode structure, where the gate insulator and semiconductor are deposited sequentially by plasma enhanced chemical vapour deposition in the same growth apparatus.Localised electron states in the amorphous silicon are crucial in determining transistor performance. Conduction band states (Si-Si antibonding σ*) are broadened and localised in the amorphous network, and their energy distribution determines the field effect mobility. The silicon dangling bond defect is the most important deep localised state and their density determines the prethreshold current and hence the threshold voltage. The density of states is influenced by the gate insulator interface and there is probably a decreasing density of states away from this interface. The silicon dangling bond defect in the bulk amorphous silicon nitride also leads to a localised gap state, which is responsible for the observed threshold voltage instability.Other key material properties include the fixed charge densities associated with primary passivating layers placed on top of the amorphous silicon. The low value of the bulk density of states in the amorphous silicon layer increases the sensitivity of device characteristics to charge at the top interface.

A GaAsMISFET using an MBE-grown CaF/sub 2/ gate insulator layer

1988 ◽  
Vol 9 (10) ◽  
pp. 548-549 ◽  
Author(s):  
T. Waho ◽  
F. Yanagawa
Keyword(s):  
Gate Insulator ◽  
Insulator Layer
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