Interfacial Adhesion Study of Porous Low-K Dielectrics to CVD Barrier Layers

2002 ◽  
Vol 716 ◽  
Author(s):  
Jeffrey A. Lee ◽  
Jeffrey T. Wetzel ◽  
Caroline Merrill ◽  
Paul S. Ho
Keyword(s):  
Mechanical Properties ◽  
Fracture Energy ◽  
Barrier Layer ◽  
Dielectric Material ◽  
Measurement Data ◽  
Dielectric Materials ◽  
Cohesive Failure ◽  
University Of Texas ◽  
Barrier Layers ◽  
Low K

AbstractThe present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 < k < 2.3). It was found that the fracture energy decreases with the dielectric constant, which correlates with mechanical properties such as Young's modulus and hardness. Adhesion measurement data was also obtained for different lowk / barrier layer interfaces. The independence of interfacial fracture energy on the type of interface suggests that cohesive failure occurs in the low-k material layer and not at the interface. In addition, the very low fracture energies (G < 3 J/2) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

The Integration of Low-k Dielectric Material Hydrogen Silsesquioxane (HSQ) with Nitride Thin Films as Barriers

2000 ◽  
Vol 612 ◽  
Author(s):  
Yuxiao Zeng ◽  
Linghui Chen ◽  
T. L. Alford
Keyword(s):  
Thin Films ◽  
Barrier Layer ◽  
Refractory Metal ◽  
Dielectric Material ◽  
Considerable Importance ◽  
Hydrogen Silsesquioxane ◽  
Barrier Layers ◽  
Vlsi Technology ◽  
Materials Used ◽  
Low K

AbstractHSQ (hydrogen silsesquioxane) is one of the promising low-k materials used in VLSI technology as an intra-metal dielectric to reduce capacitance-related issues. Like any other dielectrics, the integration of HSQ in multilevel interconnect schemes has been of considerable importance. In this study, the compatibility of HSQ with different nitride barrier layers, such as PVD and CVD TiN, PVD TaN, and CVD W2N, has been investigated by using a variety of techniques. The refractory metal barriers, Ti and Ta, are also included for a comparison. The degradation of HSQ films indicates a strong underlying barrier layer dependence. With CVD nitrides or refractory metals as barrier, HSQ exhibits a better structural and property stability than that with PVD nitrides. The possible mechanisms have been discussed to account for these observations.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

Use of Nanoindentation to Characterise the Plasma Damage Region in Low-k Dielectric Films

2006 ◽  
Author(s):  
Jon M. Molina-Aldareguia ◽  
Maria R. Elizalde ◽  
Ibon Ocan˜a ◽  
Javier Gil-Sevillano ◽  
Jose´ M. Marti´nez-Esnaola ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Depth Resolution ◽  
Dielectric Materials ◽  
Dynamical Response ◽  
Indentation Modulus ◽  
Depth Sensing ◽  
K Value ◽  
Graded Structure ◽  
Graded Structures ◽  
Low K

The thermo-mechanical robustness of interconnect structures is a key reliability concern for integrated circuits. The introduction of new low dielectric constant (low-k) materials with deteriorated mechanical strength (i.e., Young Modulus decreases exponentially with film porosity, which is needed to lower the k value of the dielectric materials) to meet the RC delay goals increase the risk of mechanical adhesive and/or cohesive failure of the device during packaging or even in service. Therefore, the mechanical properties of low-k dielectrics must be studied in detail. This is made very challenging by the fact that they have submicron thickness and that they often display a graded structure due to the damage introduced by exposure to different plasmas during processing. In this context, we demonstrate that nanoindentation is very well suited to study this type of materials. We will show how conventional depth sensing nanoindentation is of limited value to characterise the extent of the plasma induced damage because this extents just a few tens of nanometres and the graded structure can not be sampled with enough depth resolution. However, nanoindentation in modulus mapping mode can achieve enough depth resolution to characterise such nanoscale graded structures. In this technique, the electrostatic force acting on the indenter tip is sinusoidally modulated, while contact mode imaging at a very small force is performed. The dynamical response is then analyzed to extract the local indentation modulus of the sample at each pixel. By using this technique, we have depth profiled the mechanical properties of the plasma induced damage region of OSG films exposed to different plasmas, by acquiring modulus maps as a function of thickness removed in wear experiments. The results correlate well with the density depth profiles derived from X-Ray Reflectivity measurements.

Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films

2006 ◽  
Vol 914 ◽  
Author(s):  
Ryan Scott Smith ◽  
C. J. Uchibori ◽  
P. S. Ho ◽  
T. Nakamura
Keyword(s):  
Molecular Structure ◽  
Crack Growth ◽  
Adhesion Strength ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Growth Data ◽  
Critical Crack ◽  
Ambient Temperatures ◽  
Technology Roadmap ◽  
Low K

AbstractVery few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m2. Recently, a low-k dielectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m2. We investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and Fourier Transform IR Spectroscopy (FTIR). The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.

scholarly journals The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 849 ◽  
Author(s):  
Peng Xu ◽  
Zhongliang Pan ◽  
Zhenhua Tang
Keyword(s):  
Delay Time ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Dielectric Medium ◽  
Graphene Nanoribbon ◽  
Noise Voltage ◽  
Multilayer Graphene ◽  
Crosstalk Noise ◽  
Characteristic Analysis ◽  
Low K

The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

Electrical/Mechanical Properties of Porous Low-k Thin Films by Using Various Supramolecule Based Porogen

2007 ◽  
Vol 124-126 ◽  
pp. 185-188
Author(s):  
Jin Heong Yim ◽  
Young Kwon Park ◽  
Jong Ki Jeon
Keyword(s):  
Thin Films ◽  
Mechanical Properties ◽  
Electrical Properties ◽  
Pore Diameter ◽  
Dielectric Materials ◽  
Porous Films ◽  
Low Dielectric ◽  
Mechanical And Electrical Properties ◽  
Low K ◽  
Deposited Films

The porous SSQ (silsesquioxane) films were prepared by using alkoxy silyl substituted cyclodextrin (sCD) and methyl substituted cyclodextrin (tCD) based porogen. The mechanical and electrical properties of these deposited films were investigated for the applications as low dielectric materials. The mechanical properties of porous film by using sCD are worse than those by using tCD due to its high pore interconnection length. sCD templated porous films show almost constant pore diameter as a function of porogen concentration due to strong linear polymerization of the sCD molecules through polycondensation.

Effect of Dielectric Materials on Stress-Induced Damage Modes in Damascene Cu Lines

2003 ◽  
Vol 795 ◽  
Author(s):  
Jong-Min Paik ◽  
Hyun Park ◽  
Ki-Chul Park ◽  
Young-Chang Joo
Keyword(s):  
Mechanical Properties ◽  
Hydrostatic Stress ◽  
Three Dimensional ◽  
Dielectric Materials ◽  
The Other ◽  
Von Mises Stress ◽  
X Ray Diffraction ◽  
X Ray ◽  
Von Mises ◽  
Low K

ABSTRACTVarious low-k materials are being pursued as dielectric materials for future interconnects. However, poor thermo-mechanical properties of low-k materials cause tremendous reliability concerns, thus the proper materials for integration with Cu are not suggested yet. In this study, the line width and spacing dependence of damascene Cu lines embedded by TEOS and low-k materials (CORAL) was analyzed using x-ray diffraction. Generally, the hydrostatic stress of Cu/TEOS was greater than that of Cu/CORAL, while the opposite for von-Mises stress. Using a three-dimensional finite analysis (FEA), the effect of low-k materials on the stress and its distribution in via-line structures of dual damascene Cu interconnects was studied. In the case of Cu/TEOS, the hydrostatic stress was concentrated at the via and on the top of the lines, where it was suspected that the void would nucleate. On the other hand, in the via-line structures integrated with organic low-k materials, large von-Mises stress was maintained in the via. Therefore, the deformation of via, rather than voiding, may be the main failure mode in the interconnects with low-k materials.

Nondestructive Defect Imaging through Image Intensity Analysis

2007 ◽  
Author(s):  
J. Demarest ◽  
D. Bearup ◽  
A. Dalton ◽  
L. Hahn ◽  
B. Redder ◽  
...  
Keyword(s):  
Electron Beam ◽  
Dielectric Material ◽  
Natural Extension ◽  
Dielectric Materials ◽  
Intensity Analysis ◽  
Semiconductor Technology ◽  
Pixel Location ◽  
Imaging Mode ◽  
Defect Imaging ◽  
Low K

Abstract The continually shrinking dimensions of today’s semiconductor technology occasionally allow for novel approaches in imaging defects. It has become desirable to image subsurface voids prior to cross sectioning and some efforts have been made to address this need including the construction of specialized instrumentation [1]. The thickness of the metallization levels at the 65 nm technology node and smaller now allow for the use of the electron beam in a scanning electron microscope (SEM) as a material sensor. At high accelerating voltages (between 20-30 kV) in backscatter imaging mode the numerical gray level values at each pixel location can correlate to the amount of material directly under the electron beam at that location. This is particularly evident when dealing with defined geometries and material sets offering high contrast changes between materials such as those found in semiconductor technology like copper (Cu) metal and conventional dielectric materials. As a result, subsurface voids can be mapped to a reasonable representation prior to cross sectioning and precise pinpointing of the defect location in test structures can occur. This paper discusses this methodology on 65 nm technology with Cu metal lines in a low-k dielectric material for a two level metal test structure. To some extent this work represents a natural extension of a paper presented previously by the author [2].

Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines

2006 ◽  
Vol 914 ◽  
Author(s):  
Seung-Hyun Rhee ◽  
Conal E. Murray ◽  
Paul R. Besser
Keyword(s):  
Thermal Stress ◽  
Integrated Circuits ◽  
Structural Integrity ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
X Ray Diffraction ◽  
And Control ◽  
Measurement And Control ◽  
Low K

AbstractThe measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.

Sign in / Sign up

Export Citation Format

Share Document