Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films

2006 ◽  
Vol 914 ◽  
Author(s):  
Ryan Scott Smith ◽  
C. J. Uchibori ◽  
P. S. Ho ◽  
T. Nakamura
Keyword(s):  
Molecular Structure ◽  
Crack Growth ◽  
Adhesion Strength ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Growth Data ◽  
Critical Crack ◽  
Ambient Temperatures ◽  
Technology Roadmap ◽  
Low K

AbstractVery few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m2. Recently, a low-k dielectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m2. We investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and Fourier Transform IR Spectroscopy (FTIR). The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.

Optimization of Dielectric Cap Adhesion to Ultra-Low-k Dielectrics

2004 ◽  
Vol 812 ◽  
Author(s):  
Greg Spencer ◽  
Alfred Soyemi ◽  
Kurt Junker ◽  
Jason Vires ◽  
Michael Turner ◽  
...  
Keyword(s):  
Adhesion Strength ◽  
Dielectric Materials ◽  
Substantial Improvement ◽  
Film Deposition ◽  
Interface Adhesion ◽  
K Value ◽  
Layer Film ◽  
Point Bend ◽  
Low K ◽  
Deposition Conditions

AbstractIn this work, the adhesion of CVD dielectric caps to ULK MSQ spin-on dielectric materials with k values of 2.2 and 2.0, and a ULK CVD material with a k value of 2.7 is presented. A substantial improvement in cap adhesion to both the k2.2 ULK MSQ and the k2.7 ULK CVD material is demonstrated. The improvement is obtained using a low-k CVD glue material between the ULK dielectric and the subsequent cap material and/or by optimizing the CVD cap film deposition. Four-point bend measurement of adhesion strength is used to quantify the improvement in interface adhesion. The improvement in CVD cap adhesion is demonstrated to be strongly dependent upon both the glue layer film and the cap deposition conditions. While optimization of the CVD cap materials results in adequate adhesion for the k2.2 ULK MSQ, these improvements are demonstrated not to extend to the k2.0 ULK MSQ film.

Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

2006 ◽  
Author(s):  
Karan Kacker ◽  
George Lo ◽  
Suresh K. Sitaraman
Keyword(s):  
Dielectric Material ◽  
Semiconductor Industry ◽  
Cost Effective ◽  
Organic Substrate ◽  
Integrative Approach ◽  
Wafer Level ◽  
Technology Roadmap ◽  
Cte Mismatch ◽  
Compliant Interconnect ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

scholarly journals Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material

2020 ◽  
Vol 18 (2) ◽  
pp. 724
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
K. E. Kaharudin ◽  
I. Ahmad
Keyword(s):  
Performance Improvement ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Metal Gate ◽  
High Permittivity ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
High K ◽  
Low Performance ◽  
High K Dielectric

<p><span>In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance <br /> (LP) technology. </span></p>

Interfacial Adhesion Study of Porous Low-K Dielectrics to CVD Barrier Layers

2002 ◽  
Vol 716 ◽  
Author(s):  
Jeffrey A. Lee ◽  
Jeffrey T. Wetzel ◽  
Caroline Merrill ◽  
Paul S. Ho
Keyword(s):  
Mechanical Properties ◽  
Fracture Energy ◽  
Barrier Layer ◽  
Dielectric Material ◽  
Measurement Data ◽  
Dielectric Materials ◽  
Cohesive Failure ◽  
University Of Texas ◽  
Barrier Layers ◽  
Low K

AbstractThe present paper discusses the four-point bending technique employed at The University of Texas at Austin (UT Austin) to characterize adhesion strength of ultra low-k dielectric materials to CVD barrier layers. Adhesion energy between an ultra low-k dielectric material and a barrier layer was measured as a function of porosity (2.0 < k < 2.3). It was found that the fracture energy decreases with the dielectric constant, which correlates with mechanical properties such as Young's modulus and hardness. Adhesion measurement data was also obtained for different lowk / barrier layer interfaces. The independence of interfacial fracture energy on the type of interface suggests that cohesive failure occurs in the low-k material layer and not at the interface. In addition, the very low fracture energies (G < 3 J/2) confirm the weak mechanical properties of such highly porous materials. Experimental results are illustrated with analysis of failure surfaces using Auger Electron Spectroscopy and Scanning Electron Microscopy.

scholarly journals The Ultra-Low-k Dielectric Materials for Performance Improvement in Coupled Multilayer Graphene Nanoribbon Interconnects

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 849 ◽  
Author(s):  
Peng Xu ◽  
Zhongliang Pan ◽  
Zhenhua Tang
Keyword(s):  
Delay Time ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Dielectric Medium ◽  
Graphene Nanoribbon ◽  
Noise Voltage ◽  
Multilayer Graphene ◽  
Crosstalk Noise ◽  
Characteristic Analysis ◽  
Low K

The ultra-low-k dielectric material replacing the conventional SiO2 dielectric medium in coupled multilayer graphene nanoribbon (MLGNR) interconnects is presented. An equivalent distributed transmission line model of coupled MLGNR interconnects is established to derive the analytical expressions of crosstalk delay, transfer gain, and noise output for 7.5 nm technology node at global level, which take the in-phase and out-of-phase crosstalk into account. The results show that by replacing the SiO2 dielectric mediums with the nanoglass, the maximum reduction of delay time and peak noise voltage are 25.202 ns and 0.102 V for an interconnect length of 3000 µm, respectively. It is demonstrated that the ultra-low-k dielectric materials can significantly reduce delay time and crosstalk noise and increase transfer gain compared with the conventional SiO2 dielectric medium. Moreover, it is found that the coupled MLGNR interconnect under out-of-phase mode has a larger crosstalk delay and a lesser transfer gain than that under in-phase mode, and the peak noise voltage increases with the increase of the coupled MLGNR interconnect length. The results presented in this paper would be useful to aid in the enhancement of performance of on-chip interconnects and provide guidelines for signal characteristic analysis of MLGNR interconnects.

Statistics of Crack Growth of a Superalloy Under Sustained Load

1984 ◽  
Vol 106 (1) ◽  
pp. 79-83 ◽  
Author(s):  
J. N. Yang ◽  
R. C. Donath
Keyword(s):  
Growth Rate ◽  
Crack Growth ◽  
Hold Time ◽  
Creep Crack Growth ◽  
Random Variable ◽  
Compact Tension ◽  
Crack Size ◽  
Sustained Load ◽  
Growth Data ◽  
Critical Crack

A statistically-formulated fracture mechanics model for crack growth under sustained load is used to analyze crack growth data from 23 compact tension specimens of IN100, a turbojet engine disk material. The procedures characterize crack growth rates assuming that the growth rate is a lognormal random variable. The mean and standard deviation of the growth rate are determined from test data using the method of maximum likelihood. From these estimates, a lognormal creep crack growth rate model is developed from which is derived a statistical distribution of the crack size at any time. The distribution of time to reach some critical crack size is also presented. These distributions allow for the determination of the effect of hold time in the loading cycle on the life prediction of gas turbine engine disks.

Nondestructive Defect Imaging through Image Intensity Analysis

2007 ◽  
Author(s):  
J. Demarest ◽  
D. Bearup ◽  
A. Dalton ◽  
L. Hahn ◽  
B. Redder ◽  
...  
Keyword(s):  
Electron Beam ◽  
Dielectric Material ◽  
Natural Extension ◽  
Dielectric Materials ◽  
Intensity Analysis ◽  
Semiconductor Technology ◽  
Pixel Location ◽  
Imaging Mode ◽  
Defect Imaging ◽  
Low K

Abstract The continually shrinking dimensions of today’s semiconductor technology occasionally allow for novel approaches in imaging defects. It has become desirable to image subsurface voids prior to cross sectioning and some efforts have been made to address this need including the construction of specialized instrumentation [1]. The thickness of the metallization levels at the 65 nm technology node and smaller now allow for the use of the electron beam in a scanning electron microscope (SEM) as a material sensor. At high accelerating voltages (between 20-30 kV) in backscatter imaging mode the numerical gray level values at each pixel location can correlate to the amount of material directly under the electron beam at that location. This is particularly evident when dealing with defined geometries and material sets offering high contrast changes between materials such as those found in semiconductor technology like copper (Cu) metal and conventional dielectric materials. As a result, subsurface voids can be mapped to a reasonable representation prior to cross sectioning and precise pinpointing of the defect location in test structures can occur. This paper discusses this methodology on 65 nm technology with Cu metal lines in a low-k dielectric material for a two level metal test structure. To some extent this work represents a natural extension of a paper presented previously by the author [2].

Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines

2006 ◽  
Vol 914 ◽  
Author(s):  
Seung-Hyun Rhee ◽  
Conal E. Murray ◽  
Paul R. Besser
Keyword(s):  
Thermal Stress ◽  
Integrated Circuits ◽  
Structural Integrity ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
X Ray Diffraction ◽  
And Control ◽  
Measurement And Control ◽  
Low K

AbstractThe measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermal-mechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed.

Sign in / Sign up

Export Citation Format

Share Document