Nitrogen Profile Engineering in Thin Gate Oxides

1998 ◽  
Vol 525 ◽  
Author(s):  
J. Kuehne ◽  
S. Hattangady ◽  
J. Piccirillo ◽  
G. C. Xing ◽  
G. Miner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Gate Dielectrics ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Boron Penetration ◽  
Silicon Interface ◽  
Voltage Breakdown

ABSTRACTIn order to prevent boron penetration in PMOS transistors without degrading channel mobility, it is necessary to engineer the distribution of nitrogen introduced into the gate oxide. We have investigated methods of engineering this distribution using nitric oxide (NO) gas in an RTP system to thermally nitride ultra-thin gate oxides. In one approach, the gate oxide is simultaneously grown and nitrided in a mixture of nitric oxide and oxygen. For a 40 Å film, SIMS depth profiling shows that this process moves the nitrogen peak into the bulk of the oxide away from the oxide silicon interface. In another approach, an 11 Å chemical oxide produced by a standard pre-furnace wet clean is nitrided in NO at 800 deg. C. This film is subsequently reoxidized in either oxygen or steam. For an 1100 deg. C., 120 sec RTP reoxidation in oxygen, the final film thickness is 41 Å. The nitrogen has a peak concentration of 5 at. % and the peak is located in the oxide 25 Åfrom the oxide/silicon interface. Ramped voltage breakdown testing was carried out on MOS capacitors built using reoxidized NO nitrided films. They have breakdown characteristics that are equivalent to conventional furnace grown oxides. These films show considerable promise as gate dielectrics for CMOS technologies at geometries of 0.25um and below.

A Comparison of Active Near-Interface Traps in Nitrided and As-Grown Gate Oxides by the Direct Measurement Technique

2020 ◽  
Vol 1004 ◽  
pp. 635-641
Author(s):  
Peyush Pande ◽  
Sima Dimitrijev ◽  
Daniel Haasmann ◽  
Hamid Amini Moghadam ◽  
Philip Tanner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Comparative Analysis ◽  
Direct Measurement ◽  
Measurement Technique ◽  
Measurement Method ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Direct Measurement Method

This paper presents a comparative analysis of the electrically active near-interface traps, energetically located above the bottom of conduction band. Two different samples of N-type SiC MOS capacitors were fabricated with gate oxides grown in (1) dry O2 (as-grown) and (2) dry O2 annealed in nitric oxide (nitride). Measurements performed by the direct measurement method revealed that the traps located further away from the SiO2/SiC interface are removed by nitridation. A spatially localized behaviour of NITs is observed only in the nitrided gate oxide but not in the as-grown gate oxide.

Stability of Ultra-Thin Gate Oxides with Boron Doped Polysilicon Gate Structures After Rapid Thermal Annealing

1993 ◽  
Vol 303 ◽  
Author(s):  
Bojun Zhang ◽  
Dennis M. Maher ◽  
Mark S. Denker ◽  
Mark A. Ray
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Depth Profiling ◽  
Gate Oxide ◽  
Annealing Condition ◽  
Dopant Diffusion ◽  
Boron Diffusion ◽  
Gate Oxides ◽  
Diffusion Behavior ◽  
Polysilicon Gate

ABSTRACTWe report a systematic study of dopant diffusion behavior for thin gate oxides and polysilicon implanted gate structures. Boron behavior is emphasized and its behavior is compared to that of As+ and BF2+. Dopant activation is achieved by rapid thermal annealing. Test structures with 100 Å, 60 Å and 30 Å gate oxides and ion implanted polysilicon gate electrodes were fabricated and characterized after annealing by SIMS, SEM, TEM, and C-V rpeasurements. For arsenic implanted structures, no dopant diffusion through a gate oxide of 30 Å thickness and an annealing condition as high as 1 100*C/1Os was observed. For boron implanted structures, as indicated by SIMS depth profiling, structures annealed at 1000*C/10s exhibit a so-called critical condition for boron diffusion through a 30 Å gate oxide. Boron dopant penetration is clearly observed for 60 Å gate oxides at an annealing condition of 1050 0C/10s. The flatband voltage shift can be as high as 0.56 volts as indicated by C-V measurements for boron penetrated gate oxides. However, 100 Å gate oxides are good diffusion barriers for boron at an annealing condition of 1100°C/10s. For BF2 implanted structures, the diffusion behavior is consistent with behavior reported in the literature.

Characterization of Nitrided Gate Oxide Formed by RTP for SiC MOSFET Application

2011 ◽  
Vol 324 ◽  
pp. 221-224 ◽  
Author(s):  
Aurore Constant ◽  
Philippe Godignon
Keyword(s):  
Gate Oxide ◽  
Breakdown Field ◽  
Gate Oxides ◽  
Furnace Process ◽  
Surface Pretreatment ◽  
Channel Mobility ◽  
Conventional Furnace ◽  
The One

Gate oxides for SiC lateral MOSFETs have been formed in N2O by rapid thermal processing (RTP) as an alternative to the conventional furnace process. This innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to a standard oxidation, but also to produce oxide layers with quality comparable to the one grown in a conventional furnace. Moreover, a significant improvement of the oxide quality and MOSFET performance is observed when performing in-situ a H2 anneal prior to oxidation as surface pretreatment. The channel mobility and the breakdown field of the gate oxide are considerably increased.

Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Deposition Process ◽  
Gate Oxides ◽  
Boron Doped ◽  
Excellent Control ◽  
Lower Temperature ◽  
Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

Electrical Properties of High-K LaLuO3 Gate Oxide for SOI MOSFETs

2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Gate Oxide ◽  
Interface State ◽  
Channel Length ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Threshold Voltages

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.

Controlled Thin Oxidation and Nitridation in a Single Wafer Cluster Tool

1995 ◽  
Vol 387 ◽  
Author(s):  
I. Sagnes ◽  
D Laviale ◽  
F. Glowacki ◽  
B. Blanchard ◽  
F. Martin
Keyword(s):  
Surface Preparation ◽  
Gate Oxide ◽  
Dielectric Films ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Precise Control ◽  
Boron Penetration ◽  
Gate Resistance ◽  
Thin Dielectric Films ◽  
Cluster Tool

abstractFor both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

2006 ◽  
Vol 527-529 ◽  
pp. 1301-1304
Author(s):  
Mitsuo Okamoto ◽  
Mieko Tanaka ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda
Keyword(s):  
Valence Band ◽  
Oxidation Process ◽  
Gate Oxide ◽  
Interface States ◽  
Wet Oxidation ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Dry Oxidation ◽  
Low Threshold ◽  
P Type

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Comparative Studies of Gate Oxides Using Thermal, Stacked Gate, and Rapid Thermal Oxidation

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Chittipeddi ◽  
P. K. Roy ◽  
V. C. Kannan ◽  
R. Singh ◽  
C. M. Dziuba
Keyword(s):  
Thermal Oxidation ◽  
Defect Density ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Rapid Thermal Oxidation ◽  
Transmission Electron ◽  
Lattice Images ◽  
Flatband Voltage

AbstractIn this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

2000 ◽  
Vol 654 ◽  
Author(s):  
X. Duan ◽  
K. Kisslinger ◽  
L. Mayes ◽  
S. Ruby ◽  
J. Barrett
Keyword(s):  
Electron Microscopy ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Atomic Level ◽  
Electrical Performance ◽  
Interface Morphology ◽  
Gate Oxides ◽  
Mos Devices ◽  
Transmission Electron ◽  
The Impact

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

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