Ellipsometry Measurement Accuracy of Gate Oxides under Polysilicon

2003 ◽  
Vol 782 ◽  
Author(s):  
Gary Jiang ◽  
Don Pelcher ◽  
Daewon Kwon ◽  
Jana Clerico ◽  
George Collins
Keyword(s):  
Gate Dielectric ◽  
Optical Feedback ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Visible Spectral Range ◽  
Dielectric Films ◽  
High Yield ◽  
Gate Oxides ◽  
Airborne Contamination ◽  
Accuracy And Repeatability

ABSTRACTPrecisely controlling the thickness of ultrathin silicon dioxide (SiO2) gate dielectric films is critical for high yield advanced generation semiconductor manufacturing. Advanced methods for producing ultrathin gates deposit both the gate dielectric and the polysilicon (poly-Si) gate electrode in a single cluster tool. This avoids the opportunity for adsorption of molecular airborne contamination (MAC) between deposition of the two layers, but necessitates measuring gate oxide thickness through a thick poly-Si layer.Variations in poly-Si grain size, amorphous silicon content, and roughness, make it very difficult to model the optical feedback in the visible spectral range to resolve ultrathin (10–20 Å) gate oxides with sufficient accuracy and repeatability for process control.This paper studies the optical behavior of the poly-Si/dielectric filmstack from 190 nm to 900 nm and the physical properties of the poly-Si layer. A more accurate modeling method is proposed to characterize the poly-Si and its top roughness layer using effective medium approximation (EMA) models. Using the new model, both a spectroscopic ellipsometer (SE) and a multi-angle multi-wavelength laser ellipsometer (MWLE) were employed to measure wafers with different poly-Si and gate oxide thicknesses. TEM was used to characterize the film thickness while roughness was determined using AFM. Good correlation was obtained between the TEM, AFM, and ellipsometry results. Excellent repeatability (0.04 Å 1σ on a 15 Å gate oxide for 10 days) and across the wafer uniformity (0.2 Å 1σ for a 49-point map) were also achieved when measuring gate dielectric films under the poly-Si with the MWLE.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Alternate Gate Oxides for Silicon Mosfets Using High-k Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
C. A. Billman ◽  
P. H. Tan ◽  
K. J. Hubbard ◽  
D. G. Schlom
Keyword(s):  
Dielectric Constant ◽  
Thermodynamic Stability ◽  
Thermodynamic Data ◽  
Gate Dielectric ◽  
Inorganic Compounds ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Binary Oxides ◽  
High K ◽  
Ranked List

ABSTRACTHigh K (dielectric constant) and silicon-compatibility are essential for an alternative gate dielectric for use in silicon MOSFETs. Thermodynamic data were used to comprehensively evaluate the thermodynamic stability of binary oxides and binary nitrides in contact with silicon at 1000 K. Using the Clausius-Mossotti equation and ionic polarizabilities, the K of all known inorganic compounds composed of Si-compatible binary oxides was estimated. A ranked list of alternate gate oxide candidates that are likely to possess both high K and silicon-compatibility is given.

Controlled Thin Oxidation and Nitridation in a Single Wafer Cluster Tool

1995 ◽  
Vol 387 ◽  
Author(s):  
I. Sagnes ◽  
D Laviale ◽  
F. Glowacki ◽  
B. Blanchard ◽  
F. Martin
Keyword(s):  
Surface Preparation ◽  
Gate Oxide ◽  
Dielectric Films ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Precise Control ◽  
Boron Penetration ◽  
Gate Resistance ◽  
Thin Dielectric Films ◽  
Cluster Tool

abstractFor both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.

Gadolinium silicate gate dielectric films with sub-1.5 nm equivalent oxide thickness

2001 ◽  
Vol 78 (12) ◽  
pp. 1718-1720 ◽  
Author(s):  
J. A. Gupta ◽  
D. Landheer ◽  
J. P. McCaffrey ◽  
G. I. Sproule
Keyword(s):  
Gate Dielectric ◽  
Oxide Thickness ◽  
Dielectric Films ◽  
Equivalent Oxide Thickness

scholarly journals HRTEM Image Simulations for the Study of Ultrathin Gate Oxides

2002 ◽  
Vol 8 (5) ◽  
pp. 412-421 ◽  
Author(s):  
Seth T. Taylor ◽  
John Mardinly ◽  
Michael A. O'Keefe
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Structural Defects ◽  
Objective Lens ◽  
Specimen Thickness ◽  
Hrtem Image ◽  
Gate Oxides ◽  
Gate Oxide Thickness ◽  
Simulated Images ◽  
Image Simulations

We have performed high resolution transmission electron microscope (HRTEM) image simulations to qualitatively assess the visibility of various structural defects in ultrathin gate oxides of MOSFET devices, and to quantitatively examine the accuracy of HRTEM in performing gate oxide metrology. Structural models contained crystalline defects embedded in an amorphous 16-Å-thick gate oxide. Simulated images were calculated for structures viewed in cross section. Defect visibility was assessed as a function of specimen thickness and defect morphology, composition, size, and orientation. Defect morphologies included asperities lying on the substrate surface, as well as “bridging” defects connecting the substrate to the gate electrode. Measurements of gate oxide thickness extracted from simulated images were compared to actual dimensions in the model structure to assess TEM accuracy for metrology. The effects of specimen tilt, specimen thickness, objective lens defocus, and coefficient of spherical aberration (Cs) on measurement accuracy were explored for nominal 10-Å gate oxide thickness. Results from this work suggest that accurate metrology of ultrathin gate oxides (i.e., limited to several percent error) is feasible on a consistent basis only by using a Cs-corrected microscope. However, fundamental limitations remain for characterizing defects in gate oxides using HRTEM, even with the new generation of Cs-corrected microscopes.

Improved Reliability With a New Plasma Nh3 Process for 0.35μιη P+ Poly-Gate Nitrided Oxide P-Mosfet's

1996 ◽  
Vol 446 ◽  
Author(s):  
A. Bravaix ◽  
D. Vuillaume ◽  
D. Goguenheim ◽  
V. Lasserre ◽  
A. Straboni ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Barrier Properties ◽  
Oxide Thickness ◽  
Lower Amount ◽  
Interface Traps ◽  
Gate Oxides ◽  
Hot Carrier ◽  
Gate Oxide Thickness ◽  
Donor Type ◽  
Main Influence

AbstractThe electrical properties and the hot-carrier reliability of P+ poly-gate P-MOSFET's are investigated for advanced 0.35 μπι LDD CMOS technologies. It is shown that surface-channel p-devices with an optimized plasma NH3 nitrided gate-oxide have good barrier properties and electrical performances which lead to a higher hot-carrier immunity in 8nm thick nitrided gate-oxides than in pure oxides using DC and AC experiments. The AC stressing shows that reducing the gate-oxide thickness leads to a larger influence of electron detrapping inducing a stronger influence of donor type interface traps than the usual build-up of negative charges. These distinct degradation mechanisms are less significant in nitrided oxide p-MOSFET's due to the lower lateral electric field leading to a lower amount of trapped charges which are quickly suppressed during subsequent detrapping phases leaving the main influence of the interface traps.

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

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