Study of Nitrogen Incorporation in Gate Oxides Using the Resistance to Oxidation Method

Numerous nitridation processes have been studied to obtain very thin (≤ 6 nm), reproducible and reliable gate oxides. Recent results (1,2,3) have confirmed that i) the NO molecule is the species responsible for the nitrogen incorporation at the SiO2/Si interface and that ii) the direct use of NO gas allows the gate oxide to be nitrided at low thermal budget whilst maintaining the same advantages as those of N2O nitridation. NO nitridation of very thin oxides has so far been inadequately documented in terms of incorporated nitrogen concentration at the SiO2/Si interface. It is of prime importance to control the incorporation of a few nitrogen monolayers at the SiO2/Si interface, particularly for device performances in the 0. 18μm CMOS technology. In the following we present results on the control of low nitrogen concentration in pure NO atmosphere, with particular emphasis on a method based on the re-oxidation of nitrided oxides. This method can be used in a production line thus avoiding the high costs and long characterization times associated with SIMS measurements.

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Integration of NiSi SALICIDE for Deep Submicron CMOS Technologies

MRS Proceedings ◽

10.1557/proc-514-179 ◽

1998 ◽

Vol 514 ◽

Cited By ~ 8

Author(s):

X. W. Lin ◽

N. Ibrahim ◽

L. Topete ◽

D. Pramanik

Keyword(s):

Thin Films ◽

Single Crystal ◽

Sheet Resistance ◽

Thermal Annealing ◽

Cmos Technology ◽

Deep Submicron ◽

Thermal Budget ◽

Si Substrates ◽

Low Thermal Budget ◽

Lower Resistivity

ABSTRACTA NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.

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Controlled Thin Oxidation and Nitridation in a Single Wafer Cluster Tool

MRS Proceedings ◽

10.1557/proc-387-253 ◽

1995 ◽

Vol 387 ◽

Cited By ~ 1

Author(s):

I. Sagnes ◽

D Laviale ◽

F. Glowacki ◽

B. Blanchard ◽

F. Martin

Keyword(s):

Surface Preparation ◽

Gate Oxide ◽

Dielectric Films ◽

Gate Oxides ◽

Thermal Budget ◽

Precise Control ◽

Boron Penetration ◽

Gate Resistance ◽

Thin Dielectric Films ◽

Cluster Tool

abstractFor both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.

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Rapid thermal anneal of gate oxides for low thermal budget TFT's

IEEE Transactions on Electron Devices ◽

10.1109/16.737442 ◽

1999 ◽

Vol 46 (1) ◽

pp. 63-69 ◽

Cited By ~ 9

Author(s):

N. Bhat ◽

A.W. Wang ◽

K.C. Saraswat

Keyword(s):

Rapid Thermal Anneal ◽

Gate Oxides ◽

Thermal Budget ◽

Low Thermal Budget

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Electrical characterization of low thermal budget gate oxides on Si/Si0.8Ge0.2/Si substrates

Solid-State Electronics ◽

10.1016/s0038-1101(02)00032-1 ◽

2002 ◽

Vol 46 (7) ◽

pp. 991-995 ◽

Cited By ~ 2

Author(s):

Alok Sareen ◽

Ann-Chatrin Lindgren ◽

Per Lundgren ◽

Stefan Bengtsson

Keyword(s):

Electrical Characterization ◽

Gate Oxides ◽

Thermal Budget ◽

Si Substrates ◽

Low Thermal Budget

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Self-Aligned Gate Metallization Processes with Low-Thermal Budget

MRS Proceedings ◽

10.1557/proc-514-485 ◽

1998 ◽

Vol 514 ◽

Cited By ~ 1

Author(s):

X. W. Lin ◽

M. Weling

Keyword(s):

Sheet Resistance ◽

A Priori ◽

Cmos Technology ◽

Deep Submicron ◽

Complete Suppression ◽

Metal Gate ◽

Thermal Budget ◽

Cmos Transistor ◽

Novel Concept ◽

Low Thermal Budget

ABSTRACTA novel concept for CMOS transistor gate metallization is described. It is featured with Gate Cloisonné, a process consisting of dielectric deposition over frontend transistors, followed by chemical mechanical polishing to re-expose the gate pattern on a planar dielectric background. Based on this concept, two metallization schemes have been developed. One is self-aligned metal gate process, which allows for low thermal budget gate metallization with element metals such as W and Al, resulting in a very low sheet resistance (< 1 Ω/sq). The other scheme is dual self-aligned silicidation, which enables decoupling of gate silicidation from that of source/drain silicon areas. Titanium based silicidation process is implemented to form thick silicide on narrow polysilicon gates and thin one over active silicon areas. Low gate sheet resistance (≈ 1.9Ω/sq) is achieved with complete suppression of linewidth effects. Both the metallization schemes are a priori scaleable to deep submicron technologies and suitable to fabricating ultra-shallow junction devices with very low gate sheet resistance. Both of them have been implemented in a 0.25-μm CMOS technology.

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Formation of High Quality Oxynitride Gate Dielectrics by High Pressure Thermal Oxidation of Si in NO

MRS Proceedings ◽

10.1557/proc-567-65 ◽

1999 ◽

Vol 567 ◽

Cited By ~ 4

Author(s):

S. C. Song ◽

C. H. Lee ◽

H. F. Luan ◽

D. L. Kwong ◽

M. Gardner ◽

...

Keyword(s):

High Pressure ◽

Gate Dielectrics ◽

Nitrogen Concentration ◽

Budget Process ◽

High Nitrogen ◽

High Quality ◽

Thermal Budget ◽

Hot Carrier ◽

Low Thermal Budget ◽

High Nitrogen Concentration

ABSTRACTIn this paper, we report a novel low thermal budget process (<800°C) for engineered ultra thin oxynitride dielectrics with high nitrogen concentration (>5% a.c.) using vertical high pressure (VHP) process. VHP grown oxynitride films show >1 OX lower leakage current, higher drive current and superior hot-carrier reliability compared to control SiO2 of identical thickness (Tox,eq) grown by RTP in O2.

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A Two-Step, Lightly Nitrided Gate Oxidation Process For Sub-0.5 μm Cmos Technology

MRS Proceedings ◽

10.1557/proc-428-409 ◽

1996 ◽

Vol 428 ◽

Cited By ~ 2

Author(s):

P. K. Roy ◽

Y. Ma ◽

M. T. Flemming

Keyword(s):

Oxidation Process ◽

Defect Density ◽

Charge Trapping ◽

Cmos Technology ◽

Simple Extension ◽

Gate Oxides ◽

Nitrogen Incorporation ◽

Oxide Characteristics

AbstractThis work describes a two-step, lightly nitrided gate oxidation process for sub-0.5 jtm CMOS technology. This process is a simple extension of conventional oxidation using an in-situ N2O post oxidation anneal for nitrogen incorporation. Light nitrogen incorporation (∼3%) near the Si/SiO2 interface has improved oxide characteristics such as defect density (Do.), wear-out (Nbd), breakdown (Vbd) and tunneling (VFN) without altering its charge trapping behavior. Impacts of nitridation are more significant for thinner (<65Å) gate oxides (GOX).

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Impact of the Nitrogen Concentration of Sub-1.3 nm Gate Oxides on 65 nm Technology Transistor Parameters

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v2i2.265 ◽

2007 ◽

Vol 2 (2) ◽

pp. 63-66

Author(s):

A. L. Pacheco Rotondaro ◽

R. T. Laaksonen ◽

S. P. Singh

Keyword(s):

Threshold Voltage ◽

Carrier Mobility ◽

Nitrogen Concentration ◽

Hole Mobility ◽

Gate Oxide ◽

Gate Oxides ◽

Negative Shift ◽

Wide Range

The nitrogen concentration of ultrathin gate oxides (sub-1.3 nm) was varied in a wide range (from 13 % to 23 %). The threshold voltage and the channel carrier mobility of advanced 65 nm technology CMOSFET transistors fabricated with these oxides were analyzed. It was observed that increasing the nitrogen concentration in the gate oxide results in a negative shift of the threshold voltage for both NMOS and PMOS devices and a degradation of the hole mobility. It was also observed that pchannel transistors are more sensitive to the nitrogen concentration of the gate oxide than n-channel transistors.

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