Excimer Laser Crystallisation of Poly-Si TFTs for AMLCDs

2000 ◽  
Vol 621 ◽  
Author(s):  
S D Brotherton ◽  
D J McCulloch ◽  
J P Gowers ◽  
J R Ayres ◽  
C A Fisher ◽  
...  

ABSTRACTThere is interest in reducing the shot number in the poly-Si laser crystallisation process in order to improve its throughput. Two distinct shot number dependent effects have been identified, which are both laser intensity dependent. The critical laser energy density is that which causes full film melt-through, and the major issue occurs at energies greater than this, where there is a considerable degradation in device uniformity with reducing shot number. The cause of this is non-uniform recovery of the full-melt-through fine grain poly-Si, and it is demonstrated that by extending the trailing edge of the beam, the material uniformity at reduced shot number can be improved. For energies less than this, the issue is not so much uniformity, as a general degradation in overall device properties with reducing shot number, which has been correlated with reducing grain size.In more demanding, future applications (such as system-on-panel), it will be necessary to improve circuit performance and approach that of current MOSFET devices. This will require short channel, self-aligned (SA) TFTs, and some of the issues with this architecture, particularly lateral ion implantation damage beneath the gate edge and drain field relief are discussed.

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.


Crystals ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 262
Author(s):  
Mu-Chun Wang ◽  
Wen-Ching Hsieh ◽  
Chii-Ruey Lin ◽  
Wei-Lun Chu ◽  
Wen-Shiang Liao ◽  
...  

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.


1998 ◽  
Vol 532 ◽  
Author(s):  
Huilong Zhu

ABSTRACTA new physically-based model for reverse short channel effects has been developed. This kinetic model considers three species: neutral interstitial, immobile dopant and mobile interstitial-dopant pairs. To consider ion-implantation damage and stress effects on the Si/SiO2 interface, a non-uniform sink strength at the Si/SiO2 interface for interstitials has been assumed. ALAMODE, a PDE solver, was used to solve the model. Lateral boron distributions of NMOS devices in the channel near the Si/SiO2 interface have been simulated. Significant boron pile-up was found at the gate edges which is in quantitative agreement with the doping profiles extracted from experimental C-V data. The mechanism of the B diffusion in the channel region is discussed.


1980 ◽  
Vol 2 ◽  
Author(s):  
John Fletcher ◽  
J. Narayan ◽  
D. H. Lowndes

ABSTRACTThe nature and depth distributions of residual damage in ion implanted and pulsed ruby laser annealed GaAs have been studied using both plan-view and cross-section transmission electron microscopy (TEM) specimens for high dose (1.0 × 1015 cm−2) Zn+, Se+ and Mg+ implants. It was found that laser energy densities above 0.36 J/cm2 were required to remove the implantation damage, this threshold energy density giving good agreement with that indicated by electrical activation measurements. Laser induced surface degradation of the GaAs was present even for energy densities as low as 0.25 J/cm2, and more severe damage, with the introduction of dislocations near the surface, was present for energy densities above 0.8 J/cm2. The use of thin SiO2 layers for encapsulation during laser annealing was found to substantially reduce this surface degradation.


Metals ◽  
2018 ◽  
Vol 8 (8) ◽  
pp. 635 ◽  
Author(s):  
Min Zhang ◽  
Changjun Chen ◽  
Chang Liu ◽  
Shunquan Wang

This study reports the effect of Zn contents on surface morphology, porosity, microstructure and mechanical properties of laser additive manufacturing (LAM) porous ZK61 alloys. The surface morphology and porosity of the LAMed porous ZK61 alloys depend on the laser energy input. With increasing Zn contents, the surface quality of porous Mg-Zn-Zr alloys became worse, the grains are obviously refined and the precipitated phases experienced successive transitions: MgZn → MgZn + Mg7Zn3 → Mg7Zn3. The microhardness was improved significantly and ranged from 57.67 HV to 109.36 HV, which was ascribed to the fine grain strengthening, solid solution strengthening and precipitation strengthening. The LAMed porous Mg-15 wt.% Zn-0.3 wt.% Zr alloy exhibits the highest ultimate compressive strength (73.07 MPa) and elastic modulus (1.785 GPa).


Micromachines ◽  
2018 ◽  
Vol 10 (1) ◽  
pp. 6 ◽  
Author(s):  
Jürgen Lorenz ◽  
Eberhard Bär ◽  
Sylvain Barraud ◽  
Andrew Brown ◽  
Peter Evanschitzky ◽  
...  

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.


2019 ◽  
Vol 37 (1) ◽  
pp. 3-14 ◽  
Author(s):  
Guglielmo Fortunato ◽  
Massimo Cuscunà ◽  
Luca Maiolo ◽  
Luigi Mariucci ◽  
Matteo Rapisarda ◽  
...  

1998 ◽  
Vol 507 ◽  
Author(s):  
C-M Park ◽  
J-H Jeon ◽  
M-S Lim ◽  
J-S Yoo ◽  
M-K Han

ABSTRACTWe propose a novel fabrication method for a room temperature operating single-electron memory using the size and location controlled poly-Si island by lithographic technique and excimer laser annealing.We have patterned tip shaped excimer laser windows and irradiated laser energy through windows for crystallizing amorphous silicon. As a result of laser energy, the poly-Si grains are growing from patterned window side so that the fine grain and isolated large poly-Si quantum dot are inherently formed by well-known ACSLG regime. The oxidation was then performed by RTP at 950 °C for 30 seconds in order to isolate quantum island and fine poly-Si grains for quantum dot. The peaks of the poly-oxide along the poly-Si grain boundaries were lowered during that oxidation and isolated the poly-Si grains and made oxide barriers.


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