scholarly journals Design of modified booth based multiplier with carry pre-computation

2019 ◽  
Vol 13 (3) ◽  
pp. 1048
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran ◽  
Keerthana Prasad
Keyword(s):  
High Speed ◽  
High Performance ◽  
Arithmetic Unit ◽  
Verilog Hdl ◽  
Complex Arithmetic ◽  
Booth Multiplier ◽  
Embedded Computer ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Dsp Processors

Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

scholarly journals Design of High-Speed Multiplier Architecture Based on Vedic Mathematics

2018 ◽  
Vol 7 (2.4) ◽  
pp. 105
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran ◽  
Keerthana Prasad ◽  
V Siva Ramakrishna
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Expected Improvement ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Essential Components ◽  
Signal Processing Algorithms ◽  
Computational Circuits ◽  
Almost All

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

scholarly journals ASIC design of low power-delay product carry pre-computation based multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 845
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Expected Improvement ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Essential Components ◽  
Computational Circuits ◽  
Power Delay Product ◽  
Almost All

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyam sutra of Vedic Multiplication has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

Si-Ge heterojunction bipolar technology for high-speed integrated circuits

1996 ◽  
Vol 74 (S1) ◽  
pp. 159-166
Author(s):  
D. C. Ahlgren ◽  
S. J. Jeng ◽  
D. Nguyen-Ngoc ◽  
K. Stein ◽  
D. Sunderland ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Full Range ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Voltage Controlled Oscillators ◽  
Sige Hbt ◽  
Trade Offs ◽  
Scale Integration

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

An Open Architecture Control System for Parallel Kinematic Machines Based on Multi-DSP Parallel Procession

2008 ◽  
Vol 392-394 ◽  
pp. 667-671
Author(s):  
Hui Wang ◽  
Y.B. Ni ◽  
K. Li
Keyword(s):  
Control System ◽  
High Speed ◽  
High Performance ◽  
Sampling Period ◽  
Open Architecture ◽  
Accuracy Control ◽  
Communication Interface ◽  
Parallel Kinematic Machines ◽  
Parallel Kinematic ◽  
Dsp Processors

Because of the control complexity of the Parallel Kinematic Machines (PKMs), such mechanisms may suffer from lack of accuracy at high speed. Unfortunately, conventional motion controllers have very limited flexibility because they are designed for Cartesian coordinates. Therefore, the motion control system for PKMs with both high performance and open architecture is urgently demanded. In this paper, an open architecture control system for PKMs based on multi-DSP parallel procession is presented. Then, the hierarchical distributed control strategy is discussed in details. In addition, the realization of an interactive communication interface among DSP processors is presented. According to the testing results, the developed system is capable of obtaining an interpolation sampling period at least 3 times faster than that could be offered by most controllers based on single-DSP, thus it is available for high-speed and high-accuracy control of PKMs.

FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text

2013 ◽  
Vol 2 (3) ◽  
pp. 99
Author(s):  
Bharatesh N ◽  
Rohith S
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Fpga Implementation ◽  
Random Numbers ◽  
Verilog Hdl ◽  
Plain Text ◽  
Booth Multiplier ◽  
Pseudo Random Number

There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.

scholarly journals Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications

2021 ◽  
Vol 12 (3) ◽  
pp. 5673-5683
Author(s):  
Barma Venkata RamaLakshmi Et. al.
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Systems ◽  
High Demand ◽  
Major Drawback ◽  
Booth Multiplier ◽  
Computational Speed ◽  
Parallel Prefix ◽  
Simulation Results ◽  
Prefix Adders

This paper presents the implementation and design of  Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

SiGe Heterojunction Bipolar Transistors

1991 ◽  
Vol 220 ◽  
Author(s):  
Maurizio Arienzo ◽  
James H. Comfort ◽  
Emmanuel F. Crabbé ◽  
David L. Marame ◽  
Subramanian S. Iyer ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
High Performance ◽  
High Vacuum ◽  
Chemical Vapor ◽  
Layer Growth ◽  
Bipolar Transistors ◽  
Ultra High Vacuum ◽  
Ring Oscillator ◽  
Trade Offs

ABSTRACTStrained layer growth of SiGe on Si by either Molecular Beam Epitaxy (MBE) or various methods of Chemical Vapor Deposition (CVD), including Limited Reaction Processing (LRP) and Ultra High Vacuum CVD (UHV/CVD) have been used to realize narrow bandgap base double heterojunction bipolar transistors (HBTs). This review paper will focus on the fabrication of high performance transistors, and on the material and process challenges facing the implementation of SiGe HBT technology. In particular, the use of SiGe alloys for bandgap engineering of bipolar devices and the development of self-aligned, epitaxial base bipolar device structures will be discussed, including the most recent accomplishment of 75 GHz ƒr heterojunction bipolar transistors, and the record sub-25 ps EC L ring oscillator delay. The design flexibility and trade-offs offered by SiGe heterojunction technology, like junction field/capacitance control, liquid nitrogen operation and complementary processes, arc also reviewed, to assess the leverage of a SiGe base bipolar technology in high speed circuits.

scholarly journals Implementation of AMBA Based AHB2APB Bridge

2020 ◽  
Vol 8 (6) ◽  
pp. 1033-1037
Keyword(s):  
Embedded System ◽  
High Speed ◽  
High Performance ◽  
Data Loss ◽  
Verilog Hdl ◽  
Main Target ◽  
Functional Blocks ◽  
Timing Simulation ◽  
On Chip ◽  
Bus Architecture

The Advance Micro controller Bus Architecture bus protocol is used to build high performance SoC designs (system on chip). This achieves communication through the connection of different functional blocks ( or IP ). By using multiple controllers and peripherals, it makes possible to develop multiprocessor unit. It provides reusability of IP of different buses of AMBA, which can reduce the communication gap between high performance buses and low speed buses. To perform high-speed pipelined data transfers, AMBA based embedded system becomes a demanding hypothesis analytical wise, by using different bus signals supported by AMBA. To synthesize as well as simulate the composite annexation which connects advance high performance bus and advance peripheral bus which known as AHB2APB Bridge in addition to no data loss during transfer is the main target of this work. Implementation of bridge module is designed in Verilog HDL and functional and timing simulation of bridge module are done on a platform of Xilinx.

CMOS/SOS VLSI Technology

1984 ◽  
Vol 33 ◽  
Author(s):  
Tai Sato ◽  
Jun Iwamura ◽  
Hiroyuki Tango ◽  
Katsuyuki Doi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Solid Phase ◽  
Nand Gate ◽  
Gate Delay ◽  
Chip Area ◽  
Operation Speed ◽  
Vlsi Technology ◽  
Silicon Cmos ◽  
Very High

ABSTRACTCMOS is considered as a prospective technology in the VLSI era because of its low power consumption and high driving capability. While ordinary bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area, operation speed and latch-up problem due to the need for isolation wells. SOS is an inherent good partner of the CMOS circuits owing to the simple and perfect isolation. SOS technology, however, has the problem of high wafer cost. Consequently, SOS technology is best applied to high performance logic devices. Latest results of 8k-gate CMOS/SOS gate array and 16×16bit multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time, respectively, which compete with ECL devices. Application of SOS devices down to 1μm is also promising for very high speed operation. A 78ps gate delay is achieved by double solid phase epitaxy and 1μm technology. INTRO

Sign in / Sign up

Export Citation Format

Share Document