scholarly journals Ultra High MULTI CLOCK FREQUENCY BAUD RATE 128 Bit Multichannel PRBS CODEC ASIC I.P Core Design for High speed wireless internet Wi-Fi Routers, MODEM's, NIC's

2016 ◽  
Vol 3 (9) ◽  
pp. 142-149
Author(s):  
Prof P.N.V.M Sastry ◽  
Prof.Dr.D.N. Rao ◽  
Dr.S. Vathsal
Keyword(s):  
High Speed ◽  
Wireless Internet ◽  
Clock Frequency ◽  
Baud Rate

scholarly journals Design and Implementation of Power-Efficient FSM based UART

2022 ◽  
Vol 2161 (1) ◽  
pp. 012052
Author(s):  
Akshatha Kamath ◽  
Tanya Mendez ◽  
S Ramya ◽  
Subramanya G Nayak
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Total Power ◽  
Clock Frequency ◽  
General Process ◽  
Baud Rate ◽  
Power Efficient ◽  
Vlsi Chip ◽  
Finite State ◽  
Power Delay Product

Abstract The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

High Speed Wireless Internet Using LiFi

2018 ◽  
Author(s):  
Chinmay Agarwal ◽  
Medhavini Kulshrestha ◽  
Himanshu Rathore ◽  
Kamalakannan J
Keyword(s):  
High Speed ◽  
Wireless Internet

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

INVESTIGATION OF THE ABSOLUTENESS OF TIME

2021 ◽  
pp. 51-54
Author(s):  
S. Tiguntsev
Keyword(s):  
High Precision ◽  
Gravitational Potential ◽  
High Speed ◽  
Relativistic Effect ◽  
Theoretical Research ◽  
Clock Frequency ◽  
Positioning Systems ◽  
The Earth ◽  
Flow Of Time ◽  
The Difference

In classical physics, time is considered absolute. It is believed that all processes, regardless of their complexity, do not affect the flow of time The theory of relativity determines that the flow of time for bodies depends both on the speed of movement of bodies and on the magnitude of the gravitational potential. It is believed that time in space orbit passes slower due to the high speed of the spacecraft, and faster due to the lower gravitational potential than on the surface of the Earth. Currently, the dependence of time on the magnitude of the gravitational potential and velocity (relativistic effect) is taken into account in global positioning systems. However, studying the relativistic effect, scientists have made a wrong interpretation of the difference between the clock frequency of an orbiting satellite and the clock frequency on the Earth's surface. All further studies to explain the relativistic effect were carried out according to a similar scenario, that is, only the difference in clock frequencies under conditions of different gravitational potentials was investigated. While conducting theoretical research, I found that the frequency of the signal changes along the way from the satellite to the receiver due to the influence of Earth's gravity. It was found that the readings of two high-precision clocks located at different heights will not differ after any period of time, that is, it is shown that the flow of time does not depend on the gravitational potential. It is proposed to conduct full-scale experiments, during which some high-precision clocks are sent aboard the space station, while others remain in the laboratory on the surface of the earth. It is expected that the readings of the satellite clock will be absolutely identical to the readings of the clock in the Earth laboratory.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

Design and Implementation of OFDM Baseband Transmission System Based on CORDIC Algorithm and Pipeline FFT

2012 ◽  
Vol 190-191 ◽  
pp. 962-967
Author(s):  
Jun Yang ◽  
Hong Wei Ding ◽  
Ga Zhao ◽  
Ping Ping Shu
Keyword(s):  
High Speed ◽  
Transmission Rate ◽  
Adaptive Modulation ◽  
Signal Transmission ◽  
Transmission System ◽  
Cordic Algorithm ◽  
Clock Frequency ◽  
Modulation Mode ◽  
Baseband Signal ◽  
High Flexibility

This paper designed an OFDM baseband signal transmission system, which adopted CORDIC algorithm, pipeline organization and high-speed floating-point butterfly unit to complete the customized FFT Processor, and the modulation of the signal was realized by enhancing modulation mode (64-QAM) in the adaptive modulation mode. Meanwhile, due to FPGA technology is reconfigurable and parallel, the signal has a higher transmission rate. The system used FPGA resources reasonably and integrated highly, simplifying the complexity of the system; eventually it was adapted to the EP2C35F672C6 chip of Altera, and can be normally operated in the clock frequency of 100 MHz; At the same time, this system the system has high flexibility and generality, simple structure, and good clutter suppression, so it has a certain application prospects.

HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY

1995 ◽  
Vol 06 (01) ◽  
pp. 163-210 ◽  
Author(s):  
STEPHEN I. LONG
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Material Properties ◽  
High Speed ◽  
Digital Circuit ◽  
Bipolar Transistor ◽  
Clock Frequency ◽  
Digital Integrated Circuits ◽  
Heterojunction Devices ◽  
Circuit Technology

The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

scholarly journals Receiver Integration with Arrayed Waveguide Gratings toward Multi-Wavelength Data-Centric Communications and Computing

2020 ◽  
Vol 10 (22) ◽  
pp. 8205
Author(s):  
Yoshiyuki Doi ◽  
Toshihide Yoshimatsu ◽  
Yasuhiko Nakanishi ◽  
Satoshi Tsunashima ◽  
Masahiro Nada ◽  
...  
Keyword(s):  
Wavelength Division Multiplexing ◽  
High Speed ◽  
Baud Rate ◽  
Arrayed Waveguide Gratings ◽  
Wavelength Division ◽  
Integrated Devices ◽  
Multi Wavelength ◽  
Integration Techniques ◽  
Waveguide Gratings ◽  
Arrayed Waveguide

This paper reviews receivers that feature low-loss multimode-output arrayed waveguide gratings (MM-AWGs) for wavelength division multiplexing (WDM) as well as hybrid integration techniques with high-speed throughput of up to 100 Gb/s and beyond. A design of optical coupling between higher-order multimode beams and a photodiode for a flat-top spectral shape is described in detail. The WDM photoreceivers were fabricated with different approaches. A 10-Gb/s photoreceiver was developed for a 1.25-Gb/s baud rate and assembled for eight-channel WDM by mechanical alignment. A receiver with 40-Gb/s throughput was built by using visual alignment for a 10-Gb/s baud rate and four-channel WDM. A 100-Gb/s receiver assembled by active alignment with a four-channel by 25-Gb/s baud rate is the basis for beyond-100 Gb/s and future multi-wavelength integrated devices toward data-centric communications and computing.

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