Dual Tail Inverter based Comparator Design with Sub Threshold Voltage

2014 ◽  
Vol 3 (2) ◽  
pp. 33-39
Author(s):  
T. Swarna Latha ◽  
◽  
T. Suguna ◽  
Keyword(s):  
Threshold Voltage

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

2009 ◽  
Vol E92-A (4) ◽  
pp. 990-997
Author(s):  
Takaaki OKUMURA ◽  
Atsushi KUROKAWA ◽  
Hiroo MASUDA ◽  
Toshiki KANAMOTO ◽  
Masanori HASHIMOTO ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Time Variation ◽  
Transition Time ◽  
Computational Accuracy

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

2014 ◽  
Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore
Keyword(s):  
Threshold Voltage ◽  
Crystalline Silicon ◽  
Electrical Characterization ◽  
Visual Defect ◽  
Scanning Capacitance Microscopy ◽  
Device Model ◽  
Graphical Simulation ◽  
Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Current ◽  
Enhancement Mode ◽  
Recessed Gate

A 6T1C dynamic threshold voltage compensation IGZO-GOA circuit for 31-inch AMOLED display with slim border

2019 ◽  
pp. 497
Author(s):  
Yan Xue ◽  
Baixiang Han ◽  
Xian Wang ◽  
Shuai Zhou ◽  
Gary Chaw ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Dynamic Threshold ◽  
Voltage Compensation

A Novel OLED Pixel Circuit with Controllable Threshold Voltage Compensation Time

2019 ◽  
pp. 505
Author(s):  
Jung Chul Kim ◽  
Seonghwan Hong ◽  
Sujin Jung ◽  
Mihee Sin ◽  
Jun Suk Yoo ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Voltage Compensation ◽  
Pixel Circuit

Highly Reliable a-IGZO TFT Gate Driver Circuit to Suppress Threshold Voltage Shift of Pull-down TFT

2019 ◽  
pp. 1520
Author(s):  
Jungwoo Lee ◽  
Jongsu Oh ◽  
Eun Kyo Jung ◽  
KeeChan Park ◽  
Jae-Hong Jeon ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Driver Circuit ◽  
Gate Driver ◽  
Igzo Tft

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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