scholarly journals Bitstream Photon Counting Chirped AM Lidar with a Dual Unipolar Signal

2020 ◽  
Author(s):  
Brian Redman
Keyword(s):  
Integrated Circuits ◽  
Phase I ◽  
Signal To Noise Ratio ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Sinusoidal Signal ◽  
Oxide Semiconductor ◽  
Quadrature Phase ◽  
Simulation Results

This paper is a follow-up to three previous papers: the first introducing the new Bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with the unipolar Digital Logic Local Oscillator (DLLO) concept, the second introducing the improvement thereof using the bipolar DLLO, and the third introducing the improvement of digital In-phase and Quadrature-phase (I/Q) demodulation.In that previous work, the signal was a single unipolar chirped sinusoidal or square wave. This paper introduces a new bitstream PC-CAML transceiver architecture that combines two unipolar chirped signals, referred to as the dual unipolar signal, to form a single bipolar signal in the receiver. (patent pending) This bipolar signal is mixed with the bipolar DLLOs in the in-phase (I) digital mixing and quadrature-phase (Q) digital mixing channels for digital I/Q demodulation for improved signal-to-noise ratio (SNR) compared to that when using a single unipolar signal.The simulation results presented in this paper indicate an SNR improvement for the dual unipolar chirped sinusoidal signal bitstream PC-CAML compared to that of the unipolar chirped sinusoidal signal bitstream PC-CAML (both with bipolar DLLOs and digital I/Q demodulation) of from about 3 dB to about 6 dB for signals below the onset of receiver saturation, and an improvement for maximum achievable SNR of about 13 dB if the receiver is allowed to saturate.The bitstream PC-CAML with a dual unipolar signal and bipolar DLLOs with digital I/Q demodulation architecture discussed in this paper adds complexity to the transmitter and receiver compared to the architectures presented in the previous papers. Whether or not this additional complexity is worth the improved SNR will have to be decided as part of system trade studies for particular systems and their applications.However, the new architecture still retains the key advantages of the previous bitstream PC-CAML architectures since it still replaces bulky, power-hungry, and expensive wideband RF analog electronics in the receiver with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous standard PC-CAML systems.This paper introduces the dual unipolar signal and bipolar DLLOs with digital I/Q demodulation transceiver architecture for bitstream PC-CAML, and presents the initial SNR theory with comparisons to Monte Carlo simulation results.

scholarly journals Bitstream Photon Counting Chirped AM Lidar with Digital I/Q Demodulation

2020 ◽  
Author(s):  
Brian Redman
Keyword(s):  
Integrated Circuits ◽  
Single Channel ◽  
Signal To Noise Ratio ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Oxide Semiconductor ◽  
Signal To Noise ◽  
Receiver Architecture ◽  
Noise Ratio

This paper is a follow-up to two previous papers, one introducing the new bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with the unipolar Digital Logic Local Oscillator (DLLO) concept, and the other paper introducing the improvement thereof using the bipolar DLLO. In that previous work, there was only a single channel of digital mixing of the DLLO with the received photon counting signal. This paper introduces a new bitstream PC-CAML receiver architecture with an in-phase (I) digital mixing channel and a quadrature phase (Q) digital mixing channel for digital I/Q demodulation with the bipolar DLLO to improve the signal-to-noise ratio (SNR) by 3 dB compared to that for the single digital mixing channel with the bipolar DLLO and by 5.5 dB compared to that for the single digital mixing channel with the unipolar DLLO. (patent pending) The bipolar DLLO with digital I/Q demodulation architecture discussed in this paper retains the key advantages of the previous bitstream PC-CAML with a DLLO systems since it also replaces bulky, power-hungry, and expensive wideband RF analog electronics with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous PC-CAML systems. This paper introduces the bipolar DLLO with digital I/Q demodulation receiver architecture for bitstream PC-CAML and presents the initial signal-to-noise ratio (SNR) theory with comparisons to Monte Carlo simulation results.

scholarly journals Bitstream Photon Counting Chirped AM Lidar with a Digital Logic Local Oscillator

2019 ◽  
Author(s):  
Brian Redman
Keyword(s):  
Integrated Circuits ◽  
Signal To Noise Ratio ◽  
Logic Gate ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Digital Logic ◽  
Oxide Semiconductor ◽  
Photon Counting Detector ◽  
Analog Electronics

This paper introduces a new concept for the local oscillator (LO) for the Photon Counting Chirped Amplitude Modulation Lidar (PC-CAML). Rather than using a radio-frequency (RF) analog LO applied electronically either in post-detection mixing or via opto-electronic mixing (OEM) at the detector, or applied via pre-detection mixing using an optical intensity modulator as in previous systems, the new method mixes the single-bit binary counts from the photon counting detector with a single-bit binary LO using an AND binary digital logic gate. This type of LO is called the Digital Logic Local Oscillator (DLLO), and the resulting PC-CAML system is a type of bitstream lidar called bitstream PC-CAML (patent pending).The key advantage of the DLLO in the bitstream PC-CAML is that it replaces bulky, power-hungry, and expensive wideband RF analog electronics with single-bit digital logic components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous PCCAML systems.This paper introduces the DLLO for bitstream PC-CAML concept, presents the initial signal-to-noise-ratio (SNR) theory with comparisons to Monte Carlo simulation results, and makes suggestions for future work on this concept.

scholarly journals Up-Conversion Sensing of 2D Spatially-Modulated Infrared Information-Carrying Beams with Si-Based Cameras

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3610
Author(s):  
Adrián J. Torregrosa ◽  
Emir Karamehmedović ◽  
Haroldo Maestre ◽  
María Luisa Rico ◽  
Juan Capmany
Keyword(s):  
Optical Communications ◽  
Near Infrared ◽  
Nonlinear Crystal ◽  
Signal To Noise Ratio ◽  
Low Cost ◽  
Infrared Image ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Oxide Semiconductor ◽  
Free Space Optical

Up-conversion sensing based on optical heterodyning of an IR (infrared) image with a local oscillator laser wave in a nonlinear optical sum-frequency mixing (SFM) process is a practical solution to circumvent some limitations of IR image sensors in terms of signal-to-noise ratio, speed, resolution, or cooling needs in some demanding applications. In this way, the spectral content of an IR image can become spectrally shifted to the visible/near infrared (VIS/NWIR) and then detected with silicon focal plane arrayed sensors (Si-FPA), such as CCD/CMOS (charge-coupled and complementary metal-oxide-semiconductor devices). This work is an extension of a previous study where we recently introduced this technique in the context of optical communications, in particular in FSOC (free-space optical communications). Herein, we present an image up-conversion system based on a 1064 nm Nd3+: YVO4 solid-state laser with a KTP (potassium titanyl phosphate) nonlinear crystal located intra-cavity where a laser beam at 1550 nm 2D spatially-modulated with a binary Quick Response (QR) code is mixed, giving an up-converted code image at 631 nm that is detected with an Si-based camera. The underlying technology allows for the extension of other IR spectral allocations, construction of compact receivers at low cost, and provides a natural way for increased protection against eavesdropping.

Differential Polarization Imaging and Probing [DPIP]: Seeing and Probing the “Invisible”

2012 ◽  
Author(s):  
Baohua Niu ◽  
Martin von Haartman ◽  
Patrick Pardy ◽  
Mitch Sacks
Keyword(s):  
Integrated Circuits ◽  
Signal To Noise Ratio ◽  
Polarized Light ◽  
Optical Resolution ◽  
Complementary Metal Oxide Semiconductor ◽  
Infrared Emission ◽  
Oxide Semiconductor ◽  
Orthogonal Polarization ◽  
Imaging Mode ◽  
Cmos Ic

Abstract A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.

scholarly journals Bipolar Digital Logic Local Oscillator for Bitstream Photon Counting Chirped AM Lidar

2019 ◽  
Author(s):  
Brian Redman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Signal To Noise Ratio ◽  
Photon Counting ◽  
Local Oscillator ◽  
Digital Logic ◽  
Quantization Noise ◽  
Signal To Noise ◽  
Simulation Results ◽  
Noise Ratio

This paper is a follow-up to a previous paper introducing the new bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with a Digital Logic Local Oscillator (DLLO) concept. In that previous work, the DLLO was unipolar. In this paper, a new bipolar DLLO for the bitstream PC-CAML is introduced (patent pending). The bipolar DLLO retains the key advantages of the unipolar DLLO for the bitstream PC-CAML since it also replaces bulky, power-hungry, and expensive wideband RF analog electronics with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous PC-CAML systems. In addition, the bipolar DLLO improves the electrical power signal-to-noise ratio (SNR) of the bitstream PC-CAML by about 2.5 dB compared to that of the unipolar DLLO as shown by the theoretical and Monte Carlo simulation results presented in this paper. Theoretically, there should be a 3 dB improvement for the bipolar DLLO from the elimination of the signal power loss to the DC component of the intermediate frequency (IF) spectrum that occurs with the unipolar DLLO. However, this improvement is partially offset by a higher quantization noise for the bipolar DLLO compared to that of the unipolar DLLO as explained in this paper.This paper introduces the bipolar DLLO for bitstream PC-CAML concept and presents the initial signal-to-noise ratio (SNR) theory with comparisons to Monte Carlo simulation results.

Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

2021 ◽  
pp. 1-5
Author(s):  
Fang Zhu ◽  
Guo Qing Luo
Keyword(s):  
Millimeter Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Dual Band ◽  
Cmos Process ◽  
Pumping Power ◽  
Dual Mode ◽  
Dc Power

Abstract In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

scholarly journals High Dynamic Range Imaging with TDC-Based CMOS SPAD Arrays

Instruments ◽  
2019 ◽  
Vol 3 (3) ◽  
pp. 38 ◽  
Author(s):  
Majid Zarghami ◽  
Leonardo Gasparini ◽  
Matteo Perenzoni ◽  
Lucio Pancheri
Keyword(s):  
Dynamic Range ◽  
Single Photon ◽  
Photon Counting ◽  
Complementary Metal Oxide Semiconductor ◽  
High Dynamic Range ◽  
Oxide Semiconductor ◽  
Photon Flux ◽  
Integration Time ◽  
Rate Dependent ◽  
High Dynamic

This paper investigates the use of image sensors based on complementary metal–oxide–semiconductor (CMOS) single-photon avalanche diodes (SPADs) in high dynamic range (HDR) imaging by combining photon counts and timestamps. The proposed method is validated experimentally with an SPAD detector based on a per-pixel time-to-digital converter (TDC) architecture. The detector, featuring 32 × 32 pixels with 44.64-µm pitch, 19.48% fill factor, and time-resolving capability of ~295-ps, was fabricated in a 150-nm CMOS standard technology. At high photon flux densities, the pixel output is saturated when operating in photon-counting mode, thus limiting the DR of this imager. This limitation can be overcome by exploiting the distribution of photon arrival times in each pixel, which shows an exponential behavior with a decay rate dependent on the photon flux level. By fitting the histogram curve with the exponential decay function, the extracted time constant is used to estimate the photon count. This approach achieves 138.7-dB dynamic range within 30-ms of integration time, and can be further extended by using a timestamping mechanism with a higher resolution.

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