Two Unique Case Studies Performed With Photoemission Microscopy (PEM)

1996 ◽  
Author(s):  
G.F. Shade
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Current Flow ◽  
Failure Mechanisms ◽  
Analysis Time ◽  
Unique Case ◽  
Qualitative Evidence ◽  
Leakage Path

Abstract Two cases are presented where photoemission microscopy (PEM) quickly reduced the analysis time by providing qualitative evidence of the suspected failure mechanisms. In both cases, the failures were delaying product shipments and the PEM technique was a "last hope" approach where other proposals were either not successful, or were not available to the analysts. In case one, package residue caused a leakage path that was located and confirmed by PEM. The second case required the use of PEM to observe uniformity of current flow within a polysilicon region. This second analysis provided absolute evidence that the current flow was nonuniform which supported the suspected failure mechanism. It is believed that this is the first reported observation of these two emission mechanisms during a failure analysis.

Failure Analysis for Inter-Level Short in Nanometer Semiconductor Technologies

2018 ◽  
Author(s):  
Zhigang Song
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Process Variation ◽  
Failure Mechanisms ◽  
Semiconductor Technology ◽  
New Materials ◽  
Analysis Methodology ◽  
Scaling Down ◽  
Nanometer Regime

Abstract As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling

2003 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Ed Widener ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Case Studies ◽  
Failure Mode ◽  
Failure Mechanisms ◽  
Physical Analysis ◽  
Certification Programs ◽  
Current Voltage ◽  
Electrical Analysis ◽  
Cell Defect

Abstract Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

1997 ◽  
Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Packing Density ◽  
Failure Mechanisms ◽  
Potential Solution ◽  
Critical Dimensions ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Root Cause ◽  
First Time

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.

Several Failure Analysis Cases of Pressure Equipment Under the Conditions of Complex Medium Environment

2011 ◽  
Author(s):  
Xuedong Chen ◽  
Zhibin Ai ◽  
Tiecheng Yang ◽  
Zhichao Fan ◽  
Weihe Guan
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Preventive Measures ◽  
Effective Means ◽  
Failure Mechanisms ◽  
Pressure Vessels ◽  
Influential Factors ◽  
Complex Medium ◽  
Complex Environment ◽  
Failure Prevention

There are several hundred of failure cases of pressure vessels and piping in China every year. The causes for part of accidents have been clearly analyzed, and preventive measures have been taken making the similar accidents substantially reduced, but the causes for quite a few failure accidents are still not found effectively, the similar accidents is still taking place. Through study, the authors find that the major reason for deviation of failure analysis lies in that equipments are mostly operating in complex medium environment, and mutual competition may exist among multiple failure mechanisms. Sometimes changes of some influential factors may cause the dominant failure mechanism change, even leads to totally different analysis conclusions. Combining with the analysis and verification of several failure cases of pressure vessels and piping in petrochemical enterprises, the judgment method for the dominant failure mechanism under multiple failure mechanisms is discussed in this paper, which may be helpful to provide some effective means for failure prevention of pressure equipment under complex environment.

Scanning Capacitance Microscopy Application for Bipolar and CMOS Doping Issues in Semiconductor Failure Analysis

2005 ◽  
Author(s):  
Coswin Lin ◽  
Homy Ou ◽  
Chia-Hsing Chao ◽  
Shey-Shi Lu
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Cross Section ◽  
Layer By Layer ◽  
Localization Method ◽  
Scanning Capacitance Microscopy ◽  
Leakage Path ◽  
Schematic Cross Section ◽  
Power Leakage ◽  
Plane View

Abstract Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.

Electrical Failure Analysis and Characterization of Leakage Paths Leading to Single Cell Failures in 128Mbit SDRAMs

2003 ◽  
Author(s):  
M. Versen ◽  
A. Schramm
Keyword(s):  
Failure Analysis ◽  
Single Cell ◽  
Case Studies ◽  
Leakage Current ◽  
Random Access ◽  
Electrical Failure ◽  
Leakage Path ◽  
Short Summary ◽  
Order Of Magnitude

Abstract A common failure signature in dynamic random access memories (DRAMs) is the single cell failure. The charge is lost and thereby the information stored in trench capacitors can be destroyed by high resistive leakage paths. The nature of the leakage path determines the properties of the failure such as temperature-, voltage- and timing-dependencies and its stability. In this study, high resistive leakage paths were investigated and delimited from classical shorts by estimating the order of magnitude of the leakage current and by comparison to a simple resistive leakage path. Such an investigation is the basis for a defect-based test approach that leads to multiparameter tests [1]. An introduction to the problem is given in the first section, while the second section deals with the characterization of the defects in two case studies. A short summary is given in the end.

Nanoprobing-Based EBAC Technique from Backside as Well as Frontside to Isolate Logic Fails for Otherwise Non Visual Defects

2017 ◽  
Author(s):  
Sreenath Arva ◽  
Satish Kodali ◽  
Lucile Sheridan ◽  
Karthik Kalaiazhagan ◽  
Chong Khiam Oh
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Unique Case ◽  
Analysis Techniques ◽  
Visual Defects

Abstract This paper presents unique case studies describing the use of EBAC technique. Front as well as backside EBAC on relatively smaller nets is presented to isolate logic fails which are otherwise hard to capture using conventional failure analysis techniques.

On the role of tin underlays for the prevention of thermal grooving in thin gold films

1986 ◽  
Vol 44 ◽  
pp. 732-733
Author(s):  
Jin Young Kim ◽  
R. E. Hummel ◽  
R. T. DeHoff
Keyword(s):  
Thin Film ◽  
Free Surface ◽  
Grain Boundary ◽  
Beneficial Effect ◽  
Failure Mechanism ◽  
Failure Mechanisms ◽  
Distinct Advantage ◽  
Gold Films ◽  
Gold Thin Film

Gold thin film metallizations in microelectronic circuits have a distinct advantage over those consisting of aluminum because they are less susceptible to electromigration. When electromigration is no longer the principal failure mechanism, other failure mechanisms caused by d.c. stressing might become important. In gold thin-film metallizations, grain boundary grooving is the principal failure mechanism.Previous studies have shown that grain boundary grooving in gold films can be prevented by an indium underlay between the substrate and gold. The beneficial effect of the In/Au composite film is mainly due to roughening of the surface of the gold films, redistribution of indium on the gold films and formation of In2O3 on the free surface and along the grain boundaries of the gold films during air annealing.

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