Metal Slice Defect Induced Package Level Reliability Failure

2006 ◽  
Author(s):  
Mark Zhang ◽  
Scott Liao ◽  
Sanan Liang ◽  
Ricky Lou ◽  
Rock Chen ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Reliability Test ◽  
Root Cause ◽  
Corrective Actions ◽  
Test Failure

Abstract In this paper, a case of package level reliability test failure was studied. A model of “Slice Defect”, which was identified as the root cause by failure analysis, is introduced. Experiment results are presented to approve that such model is in fact correct and the corrective actions are effective.

Semiconductor Wear Out at Nuclear Power Plants

2000 ◽  
Author(s):  
James B. Riddle
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Nuclear Power ◽  
Power Plants ◽  
Nuclear Power Plants ◽  
Light Output ◽  
Analysis Techniques ◽  
Root Cause ◽  
Corrective Actions ◽  
Control Circuits

Abstract This paper will examine semiconductor wear out at San Onofre Nuclear Generation Station (SONGS). The topics will include case studies, failure mechanisms, diagnostic techniques, failure analysis techniques and root cause corrective actions. Nuclear power plants are unique in that instrumentation and control circuits are continuously energized, are periodically tested, and have been in operation for greater than 25 years. Root cause evaluations at SONGS have identified numerous semiconductor failures due to wear out. Case studies include light output deterioration in opto-isolators, junction alloying failures of transistors and integrated circuits and parametric shifts in operational amplifiers. In most cases the devices do not fail catastrophically but degraded to the point of circuit level functional failure. Failure analysis techniques include circuit analysis, board level troubleshooting to identify the degraded components. Intermittent failures require power cycling, thermal cycling, and long term monitoring to identify the responsible components. Corrective actions for semiconductor wear out at SONGS include enhanced monitoring and proactive change out of identified part types.

Failure Analysis and Process Verification of High-Density Copper ICs Used in Multichip Modules

2017 ◽  
Author(s):  
Jeremy A. Walraven ◽  
Mark W. Jenkins ◽  
Tuyet N. Simmons ◽  
James E. Levy ◽  
Sara E. Jensen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Root Cause Analysis ◽  
Multichip Modules ◽  
Cause Analysis ◽  
Process Verification ◽  
Root Cause ◽  
Corrective Actions ◽  
Silicon Vias ◽  
Metal Layers

Abstract Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area > 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.

Case Study of a DDR Loopback Test Failure Encountered on a Map Ball Grid Array Packaged Device

2017 ◽  
Author(s):  
Jose Z. Garcia ◽  
Kris Dickson
Keyword(s):  
Failure Analysis ◽  
Ball Grid Array ◽  
Analysis Techniques ◽  
Root Cause ◽  
Test Methodology ◽  
Cause Of Failure ◽  
Test Failure

Abstract This paper describes how a DDR loopback test failure was analyzed successfully after being repackaged from an MBGA into a TBGA package substrate. DDR loopback test methodology is discussed as well as the advanced failure analysis techniques that were used to identify the root cause of failure.

Silicon Dislocation Enhanced by Dynamic Voltage Stress

2007 ◽  
Author(s):  
Yu-Cheng Lin ◽  
Rock Chen ◽  
Sanan Liang ◽  
Scott Liao ◽  
Chorng Niou ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Substrate ◽  
Reliability Test ◽  
Final Test ◽  
Functional Failure ◽  
Root Cause ◽  
Voltage Stress ◽  
Dynamic Voltage ◽  
Lightly Doped Drain ◽  
The Relationship

Abstract In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.

Wire-Wound Resistor Investigation—A Case Study

2016 ◽  
Author(s):  
Jason Wheeler ◽  
John Wolfgong
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Interesting Case ◽  
Cause Analysis ◽  
Root Cause ◽  
Resistive Element ◽  
Primary Driver ◽  
Mission Critical ◽  
Corrective Actions

Abstract The focus of this paper is to present an interesting case study involving Vishay wire-wound (WSC model) resistor failures, which affected a significant number of production and fielded assemblies. The failures were considered “mission critical”, which was the primary driver necessitating root cause analysis. A disciplined approach to the failure analysis effort was established, which resulted in root cause determination and the generation of appropriate corrective actions. This paper will highlight a non-conventional decapsulation method used to preserve the integrity of the fragile resistive element and a “lucky break” that was instrumental in linking the supplier’s actions to the failures.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

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