State of the Art Substrate Manipulation as a Tool for Enhancing Product Performance

2011 ◽  
Author(s):  
Michael A. Gonzales ◽  
Jose Cabanillas
Keyword(s):  
Integrated Circuit ◽  
Uv Light ◽  
Turnaround Time ◽  
Product Performance ◽  
Circuit Board ◽  
Conformal Coating ◽  
Root Cause ◽  
Light Curing ◽  
The Difference ◽  
Ic Package

Abstract Substrate modifications on the Integrated Circuit (IC) package provide opportunities for the Failure Analyst (FA) to troubleshoot a routing failure or allow a design engineer to create new routing possibilities for a prototype device. The results can mean the difference in finding the root cause of the problem and being early or late to market. This paper describes a variety of methods to open sections of the package circuit board to access and cut I/O traces interwoven throughout the package substrate. It also describes the use of conductive epoxies for connecting traces, vias and solders bumps. Restoring the solder mask with an ultraviolet (UV) light curing conformal coating is also discussed. This method was used to characterize ground sensitivities and simulate inductance effects on the package. The flexibility and fast turnaround time this method enables has already enhanced product performance.

scholarly journals Elevated Standoff Heights of Solder Joint Interconnections Can Result in Appreciable Stress and Warpage Relief

2019 ◽  
Vol 16 (1) ◽  
pp. 13-20
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
Reza Ghaffarian
Keyword(s):  
Solder Joint ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Calculated Data ◽  
Circuit Board ◽  
Stress Model ◽  
Solder Material ◽  
The Difference ◽  
Ic Package

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.

Design and Test of a MEMS Accelerometer Array for Submarine Landslide Displacement Monitoring

2021 ◽  
Vol 55 (1) ◽  
pp. 5-16
Author(s):  
Yongqiang Ge ◽  
Jiawang Chen ◽  
Chen Cao ◽  
Jiamin He ◽  
Yan Sheng ◽  
...  
Keyword(s):  
Gas Hydrate ◽  
Integrated Circuit ◽  
Slope Failure ◽  
Circuit Board ◽  
Measurement Unit ◽  
Physical Model Test ◽  
Submarine Landslides ◽  
Micro Electro Mechanical Systems ◽  
Mems Accelerometer ◽  
The Difference

AbstractSubmarine landslides in gas hydrate areas are a significant geo-hazard that can cause considerable damage. The processes and mechanism of submarine landslides caused by gas hydrate dissociation are not clearly understood. Therefore, we designed a micro-electro-mechanical systems (MEMS) accelerometer array to study and monitor the deep displacement of submarine landslides. The MEMS accelerometer array consists of several gravity acceleration-sensing units that are protected and positioned using a flexible circuit board and elastic steel tape, such that all the units are connected to an Inter-Integrated Circuit (IIC) communication bus. By sensing the three-axis tilt angles, the direction and magnitude of the displacement for a measurement unit can be calculated; then, the overall displacement of the array is calculated as the difference in the displacements from the initial values. To ensure the accuracy of the tilt angle and displacement calculation, the calibration and verification test of the single MEMS sensor and sensor array is conducted. The MEMS accelerometer array is verified with respect to its principle and arrangement by a laboratory physical model test, and the initial experimentation demonstrated the capacities of the monitoring system for collecting real-time and in-situ information about the dynamic process and propagation of slope failure.

Application of B-Scan SAT Mode, an Acoustic Cross Section Technique to Analyze Packaged Components beyond Delamination

2020 ◽  
Author(s):  
Srinath Rajaram ◽  
Denise Barrientos ◽  
Nadia Ahmad ◽  
Robert Carpenter ◽  
Eric Barbian
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Turnaround Time ◽  
Destructive Testing ◽  
Cross Sectional ◽  
Root Cause ◽  
Section Technique ◽  
Customer Returns ◽  
Tomography Method ◽  
Non Destructive

Abstract Failure Analysis labs involved in customer returns always face a greater challenge, demand from customer for a faster turnaround time to identify the root cause of the failure. Unfortunately, root cause identification in failure analysis is often performed incompletely or rushing into destructive techniques, leading to poor understanding of the failure mechanism and root-cause, customer dissatisfaction. Scanning Acoustic Tomography (SAT), also called Scanning Acoustic Microscope (SAM) has been adopted by several Failure Analysis labs because it provides reliable non-destructive imaging of package cracks and delamination. The SAM is a vital tool in the effort to analyze molded packages. This paper provides a review of non-destructive testing method used to evaluate Integrated Circuit (IC) package. The case studies discussed in this paper identifies different types of defects and the capabilities of B-Scan (cross-sectional tomography) method employed for defect detection beyond delamination.

Acoustic microscopy techniques for the inspection of integrated circuit devices and packages

1992 ◽  
Vol 50 (2) ◽  
pp. 966-967
Author(s):  
Thomas M. Moore
Keyword(s):  
Integrated Circuit ◽  
Acoustic Microscopy ◽  
Hybrid Technique ◽  
Frequency Scanning ◽  
Ic Packaging ◽  
Ic Package ◽  
Microscopy Techniques ◽  
Ic Package Inspection ◽  
Pulse Echo ◽  
Scanning Acoustic Microscope

In the last decade, a variety of characterization techniques based on acoustic phenomena have come into widespread use. Characteristics of matter waves such as their ability to penetrate optically opaque solids and produce image contrast based on acoustic impedance differences have made these techniques attractive to semiconductor and integrated circuit (IC) packaging researchers.These techniques can be divided into two groups. The first group includes techniques primarily applied to IC package inspection which take advantage of the ability of ultrasound to penetrate deeply and nondestructively through optically opaque solids. C-mode Acoustic Microscopy (C-AM) is a recently developed hybrid technique which combines the narrow-band pulse-echo piezotransducers of conventional C-scan recording with the precision scanning and sophisticated signal analysis capabilities normally associated with the high frequency Scanning Acoustic Microscope (SAM). A single piezotransducer is scanned over the sample and both transmits acoustic pulses into the sample and receives acoustic echo signals from the sample.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

Temperature and Humidity Dependent Reliability Analysis of RGB LED Chips

2006 ◽  
Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris
Keyword(s):  
Reliability Analysis ◽  
Printed Circuit Board ◽  
Light Emitting Diode ◽  
Circuit Board ◽  
Light Emitting ◽  
Printed Circuit ◽  
Root Cause ◽  
Micro Cracks ◽  
Temperature And Humidity

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

Evolution of Stress During Formation of Titanium Disilicide by Rta and Tube Furnace Annealing

1990 ◽  
Vol 202 ◽  
Author(s):  
J.F. Jongste ◽  
O.B. Loopstra ◽  
G.C.A.M. Janssen ◽  
S. Radelaar
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Reaction Rates ◽  
Titanium Disilicide ◽  
Furnace Annealing ◽  
Integrated Circuit Fabrication ◽  
Annealing Step ◽  
Circuit Fabrication ◽  
The Difference ◽  
Processing Steps

Integrated circuit fabrication consists of many processing steps: e.g. lithography, etching, implantation and metallization. Some of these processes are combined with thermal processing. Heat treatments require special attention because previous fabrication steps may be influenced: e.g. dopant profiles may be deteriorated. The amount of interference of an annealing step with a former process is determined by the ratio of the reaction rates (and hence by the difference in activation energies).

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