Impacts of Sample Preparation Methodology on TEM Failure Analysis of Advanced Semiconductor Devices

2011 ◽  
Author(s):  
Yongkai Zhou ◽  
Jie Zhu ◽  
Han Wei Teo ◽  
ACT Quah ◽  
Lei Zhu ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Thickness Measurement ◽  
Interface Roughness ◽  
Silicide Formation ◽  
Cross Sectional ◽  
Inspection Method ◽  
Low Mass

Abstract In this paper, two failure analysis case studies are presented to demonstrate the importance of sample preparation procedures to successful failure analyses. Case study 1 establishes that Palladium (Pd) cannot be used as pre-FIB coating for SiO2 thickness measurement due to the spontaneously Pd silicide formation at the SiO2/Si interface. Platinum (Pt) is thus recommended, in spite of the Pt/SiO2 interface roughness, as the pre-FIB coating in this application. In the second case study, the dual-directional TEM inspection method is applied to characterize the profile of the “invisible” tungsten residue defect. The tungsten residue appears invisible in the planeview specimen due to the low mass-thickness contrast. It is then revealed in the cross-sectional TEM inspection.

Case Study Failure Analysis of an Ultra-High Vacuum Enclosure Made of a Silicon Chip and Borosilicate Glass for the Cold Atom Laboratory

2017 ◽  
Author(s):  
Gil Garteiz ◽  
Javeck Verdugo ◽  
David Aveline ◽  
Eric Williams ◽  
Arvid Croonquist ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Borosilicate Glass ◽  
High Vacuum ◽  
Cold Atom ◽  
Fault Isolation ◽  
Ultra High Vacuum ◽  
Liquid Bath

Abstract In this paper, a failure analysis case study on a custom-built vacuum enclosure is presented. The enclosure’s unique construction and project requirement to preserve the maximum number of units for potential future use in space necessitated a fluorocarbon liquid bath for fault isolation and meticulous sample preparation to preserve the failure mechanism during failure analysis.

Lock-in Thermography for Flip-Chip Package Failure Analysis

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Jeffery Huynh ◽  
Joseph Tan ◽  
Meng-Yeow Tay ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Flip Chip ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Lock In

Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

Specific Area Planar and Cross-Sectional Lift-Out Techniques: Procedures and Novel Applications

2000 ◽  
Author(s):  
Raghaw S. Rai ◽  
Swaminathan Subramanian ◽  
Stewart Rose ◽  
James Conner ◽  
Phil Schani ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Specific Area ◽  
Cross Sectional ◽  
Site Specific ◽  
Focussed Ion Beam ◽  
Lattice Images ◽  
Novel Applications

Abstract Conventional focussed ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

Tri-Directional TEM Failure Analysis on Sample Prepared by In-Situ Lift-Out FIB and Flipstage

2014 ◽  
Author(s):  
Jie Zhu ◽  
An Yan Du ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
Si Ping Zhao ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Root Cause Analysis ◽  
Wafer Surface ◽  
Tem Analysis ◽  
Cause Analysis ◽  
Root Cause

Abstract In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.

Failure Analysis of Advanced Microprocessors through Backside Approaches

1998 ◽  
Author(s):  
D. Davis ◽  
O. Diaz de Leon ◽  
L. Hughes ◽  
S. V. Pabbisetty ◽  
R. Parker ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Preparation Methods ◽  
Analysis Techniques ◽  
Analytical Approaches ◽  
Sample Preparation Methods ◽  
New Devices

Abstract The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.

Case Study—Lock-in Thermography Application in Failure Analysis of a System Level DC-DC μModule Regulator

2017 ◽  
Author(s):  
Vikash Kumar ◽  
Devraj Karthikeyan
Keyword(s):  
Heat Source ◽  
Failure Analysis ◽  
Case Studies ◽  
Fault Localization ◽  
System Level ◽  
Thermal Failure ◽  
Analysis Process ◽  
Lock In

Abstract Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator

Case Studies of the Use of Image Processing in Metrology and Failure Analysis

2005 ◽  
Author(s):  
Kartik Ramanujachar
Keyword(s):  
Image Processing ◽  
Failure Analysis ◽  
Case Studies ◽  
Nearest Neighbor ◽  
Image Data ◽  
Cumulative Distribution ◽  
Information Theoretic ◽  
Atomic Force ◽  
Processing Techniques

Abstract This paper describes the use of image processing techniques in metrology and failure analysis with the help of three case studies. The first study concerns a technique that significantly automates the process and hence enables both a rapid and accurate extraction of cumulative distribution function for transistor CD through the use of edge detection and quantification of image intensities. The second study is about utilizing a cross correlation algorithm and an appropriately chosen sample and image to estimate the "on image" spatial resolution of an scanning electron microscope. The last case study uses image data acquired with an atomic force microscope. The paper describes how information theoretic concepts like entropy and mutual information combined with image segmentation and nearest neighbor extraction can be used to isolate those regions of the AFM scan that can potentially benefit from further analysis.

Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices

2004 ◽  
Author(s):  
Dat Nguyen ◽  
Thao To ◽  
Ray Harrison ◽  
Cuong Phan ◽  
John Drummond
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Front Side ◽  
Defect Identification ◽  
Automated Test Equipment ◽  
Special Analysis ◽  
Failure Correlation ◽  
Similar Sample

Abstract Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

The Challenge and Methods of TEM Cross-Sectioning of < 0.25 Micron Plugs

1998 ◽  
Vol 523 ◽  
Author(s):  
C. Amy Hunt ◽  
Yuhong Zhang ◽  
David Su
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Section ◽  
Adhesion Layer ◽  
Cross Sectional ◽  
Transmission Electron ◽  
Sectional Plane ◽  
Preparation Techniques

AbstractTransmission electron microscopy (TEM) is a useful tool in process evaluation and failure analysis for semiconductor industries. A common focus of semiconductor TEM analyses is metalization vias (plugs) and it is often desirable to cross-section through a particular one. If the cross-sectional plane deviates away from the center of the plug, then the thin adhesion layer around the plug will be blurred by surrounding materials such as the inter-layer dielectric and the plug material. The importance of these constraints, along with the difficulty of precision sample preparation, has risen sharply as feature sizes have fallen to 0.25 μm and below. The suitability of common sample preparation techniques for these samples is evaluated.

Metallurgical Failure Analysis-Few Case Studies

2012 ◽  
Vol 710 ◽  
pp. 695-700
Author(s):  
Sushant K. Manwatkar ◽  
M. Swathi Kiranmayee ◽  
Abhay Kumar Jha ◽  
P. Ramesh Narayanan ◽  
K. Sreekumar ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Material Science ◽  
Material Selection ◽  
Fatigue Loading ◽  
The Other ◽  
Induced Stress ◽  
Analytical Tools ◽  
Causes Of Failure

Advancement in material science has reached great heights both in terms of development and properties but still failures continue to happen. Failure is often accompanied by economic and human loss. Failures generally occur due to error of knowledge, error of performance and error of intent which comprises improper design and/or material selection, deficiency in processing and assembly. Failure analyst plays an important role in evaluating the causes of failure by using various analytical tools to arrive at the conclusion and suggests remedies to avoid its reoccurrence. This paper highlights the important steps in failure analysis with a few case studies demonstrated. Case studies include the failure of plumbing tube used in engine gimbal control system of liquid propulsion system, where failure was initiated due to process deficiency and its propagation was facilitated under fatigue loading. In the other case study discussed, failure of steel fasteners was due to hydrogen induced stress corrosion cracking (HISCC).

Sign in / Sign up

Export Citation Format

Share Document