Simple and Effective Technique of Backside Deprocessing of Thin Flip Chip Package

Author(s):  
Suk Ho Lee ◽  
Chan Hee Park ◽  
Seung Joon Cha ◽  
Eun Cheol Lee ◽  
Kyu Shik Hong

Abstract This paper introduces a simple and effective technique of backside de-processing procedure. This technique reduces time and steps by simple wet etching. The front-side deprocessing requires many steps, such as wet and dry etching and parallel lapping, and also backside de-processing requires mechanical grinding to thin down the silicon thickness before wet etching. This paper introduces an effective way by skipping mechanical grinding and by etching at high temperature in case of thin flip chip. The backside silicon images are presented and compared after de-processing with TMAH and KOH which commonly have been used for bulk silicon etchant. The results show uniform backside images without any damage or residue. This backside de-processing technique was applied in two case studies to facilitate failure analysis.

Author(s):  
Fei Long Xu ◽  
Phoumra Tan ◽  
Dan Nuez

Abstract Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.


Author(s):  
Raymond Lee ◽  
Nicholas Antoniou

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.


Author(s):  
Chun Ming Tsai ◽  
Yi Shiuan Huang ◽  
Ya Hui Lu ◽  
Jian Chang

Abstract Backside FIB circuit edit is an effective way to modify circuit on flip chip or stacked chips. Directly damaging memory cell through bulk silicon by FIB can be used to locate bit address to verify that the scramble test program coordinates correspond to the physical cell location. This paper presents the application of FIB for chip editing, discusses the limitation of the FIB approach and reports the scramble test experiments about the front-side and backside FIB technique to correct scramble testing data.


Author(s):  
D. Vallett ◽  
J. Gaudestad ◽  
C. Richardson

Abstract Magnetic current imaging (MCI) using superconducting quantum interference device (SQUID) and giant-magnetoresistive (GMR) sensors is an effective method for localizing defects and current paths [1]. The spatial resolution (and sensitivity) of MCI is improved significantly when the sensor is as close as possible to the current paths and associated magnetic fields of interest. This is accomplished in part by nondestructive removal of any intervening passive layers (e.g. silicon) in the sample. This paper will present a die backside contour-milling process resulting in an edge-to-edge remaining silicon thickness (RST) of < 5 microns, followed by a backside GMR-based MCI measurement performed directly on the ultra-thin silicon surface. The dramatic improvement in resolving current paths in an ESD protect circuit is shown as is nanometer scale resolution of a current density peak due to a power supply shortcircuit defect at the edge of a flip-chip packaged die.


2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.


2015 ◽  
Vol 821-823 ◽  
pp. 541-544 ◽  
Author(s):  
Yong Zhao Yao ◽  
Yukari Ishikawa ◽  
Yoshihiro Sugawara ◽  
Koji Sato

To remove the surface damages induced during mechanical polishing (MP) of 4H-SiC, a variety of wet etching recipes and etching conditions were studied. By evaluating the epilayers grown on these etching-treated wafers, it has been found that triangular defects (TRDs) are the main defects originated from the MP-induced damages in these samples. High temperature molten KCl etching at 1100 °C with KOH additive is very effective to remove the damaged surface while keeping a relatively flat surface. Epilayer grown on the KCl+KOH etched wafer showed a TRD density <0.9 cm-2.


2017 ◽  
Vol 2017 (HiTEN) ◽  
pp. 000031-000035 ◽  
Author(s):  
R. Bannatyne ◽  
D. Gifford ◽  
K. Klein ◽  
K. McCarville ◽  
C. Merritt ◽  
...  

Abstract This paper will describe the development and testing of a new ARM© Cortex©-M based microcontroller for high temperature electronic systems. High temperature and electrical overstresses can cause latch-up in CMOS devices that will interfere with normal device operation or destroy the device. For reliable operation in the downhole drilling environment it was necessary to immunize this device against latch-up using an innovation processing technique. HARDSIL® technology that allows reliable latch-up free operation at extreme temperatures will be described. Details on the qualification and testing of the product to ensure that it meets the challenging environment will also be discussed. This includes electrical testing and temperature cycling testing to ensure that the different package options for the silicon device are mechanically sound in a high temperature environment that exposes the silicon and packaging materials to thermal cycling. The ecosystem for the microcontroller will also be discussed – hardware and software development tools are required to optimize the use of the device in extreme temperature embedded systems. An ecosystem of components is also required to operate with the microcontroller in the high temperature harsh environment.


2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002481-002506
Author(s):  
Mathias Nowottnick ◽  
Andreas Fix

The electromigration effects in chip metallization and wire bonds are well known and detailed investigated. Current density could be extremely high because of the small size of the cross sectional area of conductors. This can cause a migration of metal atoms toward the electrical field, so current densities up to 106 A/cm2 are possible. In comparison with chip structures are the usual solder joints of flip chips relatively thick. But the homologue temperature of solder alloys, typically based on tin, is also much higher than for gold or aluminum wires. For instance a SAC solder alloy is naturally preheated up to 0.6 homologue temperature, for high temperature application with 125 °C operating temperature even more than 0.8. This means, that atoms are very agile and a directed movement needs only lower field strength. Additionally is the specific resistance of solder alloys tenfold higher than for aluminum, copper or silver. So is the self-heating of solder joints not negligible. This contribution shows the test results of flip-chip assemblies, loaded with different current densities and stored at 125 °C ambient temperature. At the end of life of a significant number of test chips, a metallographic analysis shows the causing failure effects and weak spots of assemblies. Accompanying simulations help to explain the interaction between current density and migration effects.


2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.


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