Failure Analysis Methodology on Systematic Missing Cu in RAM Due to Cu CMP

2014 ◽  
Author(s):  
Ghim Boon Ang ◽  
Changqing Chen ◽  
Hui Peng Ng ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Removal Rate ◽  
Deep Dive ◽  
The Real ◽  
Root Cause ◽  
Analysis Methodology ◽  
Strong Emphasis ◽  
Cu Cmp

Abstract This paper places a strong emphasis on the importance of applying Systematic Problem Solving approach and use of appropriate FA methods and tools to understand the “real” failure root cause. A case of wafer center cluster RAM fail due to systematic missing Cu was studied. It was through a strong “inquisitive” mindset coupled with deep dive problem solving that lead to uncover the actual root cause of large Cu voids. The missing Cu was due to large Cu void induced by galvanic effects from the faster removal rate during Cu CMP and subsequently resulted in missing Cu. This highlights that the FA analyst’s mission is not simply to find defects but also play a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically/ physically) to Fab.

Device Characterization Using AFP Nanoprobing for the Localization of New Product Design Weakness

2013 ◽  
Author(s):  
Ghim Boon Ang ◽  
Alfred Quah ◽  
Changqing Chen ◽  
Si Ping Zhao ◽  
Dayanand Nagalingam ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Product Design ◽  
New Product ◽  
Analysis Tool ◽  
Deep Dive ◽  
Root Cause ◽  
Strong Emphasis ◽  
New Product Design ◽  
Testing Issue

Abstract This paper illustrated the beauty of AFP nano-probing as the critical failure analysis tool in localizing new product design weakness. A 40nm case of HTOL Pin Leakage due to Source/Drain punch-through at a systematic location was discussed. The root cause and mechanism was due to VDS overdrive testing issue. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.

Failure Analysis Methodology on Systematic Defect in ADC_PLL Ring Pattern Due to Plasma De-Chuck Process

2010 ◽  
Author(s):  
Ang Ghim Boon ◽  
Chen Changqing ◽  
Alfred Quah ◽  
Magdeliza ◽  
Indahwan Jony ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Root Cause ◽  
Path Tracing ◽  
Analysis Methodology ◽  
Wafer Fab ◽  
Problem Solving Process

Abstract In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.

Failure Analysis Methodology on Systematic Polar Failing Pattern Due to Higher Solder Bump Resistance Issue in RF SOI Device

2016 ◽  
Author(s):  
Ghim Boon Ang ◽  
Chen Changqing ◽  
Hui Peng Ng ◽  
Alfred Quah ◽  
Nagalingam Dayanand ◽  
...  
Keyword(s):  
Problem Solving ◽  
Real Root ◽  
Solder Bump ◽  
Limited Information ◽  
Deep Dive ◽  
The Real ◽  
Root Cause ◽  
Analysis Methodology ◽  
Solder Bumps ◽  
Depth Analysis

Abstract This paper placed a strong emphasis on the importance of applying Systematic Problem Solving approach, deep dive and use of right/appropriate FA approach/tools that are essentially critical to FA analysts to understand the “real” root cause. A case of low yield with polar failing pattern was seen and matched well with the Al Pad etch E chuck configuration. Customer also reported of passivation crack issue at the solder bumps. All these evidences suggested the root cause was related to wafer fabrication issue. However, it was through a strong “inquisitive” mindset coupled with the essence of such strong problem solving approach that led to uncover the actual root cause. Although customer test condition was not able to be duplicated due to limited information available in foundry industry, a four point probing alternative method was engaged to overcome this limitation. Unlike typical case, the AlOx thickness was comparable for bad and good dies. Further in depth analysis subsequently revealed the higher O content in the AlOx for the bad dies that was the real culprit for the higher bump resistance. This paper highlights the job of FA analyst is not simply finding defect but also plays a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically / physically) to Fab. It would serve as a good reference to wafer Fab that encountered such issue.

Failure Analysis Methodology on Unique 68mm Single Ring Pattern Due to Load Lock Burr

2011 ◽  
Author(s):  
A.C.T Quah ◽  
G. B. Ang ◽  
C. Q. Chen ◽  
David Zhu ◽  
M. Gunawardana ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Pattern ◽  
Root Cause ◽  
Analysis Methodology ◽  
Single Ring ◽  
Memory Failure

Abstract This paper describes a low yield case which results in a unique 68 mm single ring wafer sort failure pattern. A systematic problem solving approach with the application various FA techniques and detailed Fab investigation resolved the issue. The root cause for the unique ring failure pattern was due to a burr at the implanter load lock. The burr scratched and toppled the photoresist resulting in subsequent blocked well implantation and memory failure.

A Logical Problem Solving Process for High Via Resistance Root Cause Analysis

2008 ◽  
Author(s):  
K. Li ◽  
P. Liu ◽  
J. Teong ◽  
M. Lee ◽  
H. L. Yap
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
High Resistance ◽  
Cause Analysis ◽  
Logical Problem ◽  
Root Cause ◽  
Analysis Process ◽  
Problem Solving Process

Abstract This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.

Failure Analysis Methodology on Systematic Defect in N+ poly/NWELL Varactor in RF Analog_PLL due to Implanter Charging Issue

2012 ◽  
Author(s):  
Ang Ghim Boon ◽  
Chen Changqing ◽  
Ng Hui Peng ◽  
Neo Soh Ping ◽  
Magdeliza G ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Gate Oxide ◽  
Oxide Breakdown ◽  
Root Cause ◽  
Path Tracing ◽  
Analysis Methodology ◽  
Problem Solving Process ◽  
Access To Data ◽  
Analog Circuitry

Abstract In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

1997 ◽  
Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Packing Density ◽  
Failure Mechanisms ◽  
Potential Solution ◽  
Critical Dimensions ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Root Cause ◽  
First Time

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.

Understanding the Cu Void Formation by TEM Failure Analysis

2014 ◽  
Author(s):  
Binghai Liu ◽  
Jie Zhu ◽  
Changqing Chen ◽  
Eddie Er ◽  
Siping Zhao ◽  
...  
Keyword(s):  
Electron Diffraction ◽  
Failure Analysis ◽  
Seed Layer ◽  
Void Formation ◽  
Surface Oxidation ◽  
Alkaline Condition ◽  
Electron Diffraction Analysis ◽  
Root Cause ◽  
Cu Cmp

Abstract In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

Nanoprobing as an Essential and Fast Methodology in Identification of Failure’s Root Cause for Advanced Technology

2013 ◽  
Author(s):  
Yinzhe Ma ◽  
Chong Khiam Oh ◽  
Ohnmar Nyi ◽  
Chuan Zhang ◽  
Donald Nedeau ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Failure Mechanism ◽  
Turnaround Time ◽  
Advanced Technology ◽  
Electrical Behavior ◽  
Root Cause ◽  
Front End

Abstract This paper highlights the use of nanoprobing as a crucial and fast methodology for failure analysis (FA) in sub 20nm with an improved semi-auto nanoprobing system. Nanoprobing has the capability to localize as well as characterize the electrical behavior of the malfunctioning device for a better understanding of the failure mechanism. It provides a valuable guide to choose a proper physical FA technique to identify the root cause of the failure. This established methodology helps to accelerate the FA turnaround time and improve the success rate. Its application to a few of the front end of line and one back end of line issues is highlighted in the paper.

Humidity-Bias Driven Shorts in Multilayer Circuits: A Case Study in Failure Analysis

2000 ◽  
Author(s):  
Hei-Ruey Harry Jen ◽  
Gerald S. D’Urso ◽  
Harold Andrews
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Layer Structure ◽  
Molding Compound ◽  
Plastic Molding ◽  
Root Cause ◽  
Plastic Package ◽  
Processing Procedure ◽  
Failure Site

Abstract When a failure analysis (FA) involves a multiple layer structure separated by a polymeric material such as Benzocyclobutene (BCB), in a plastic package, it becomes a very challenging task to find out where the failure site is and how it failed. This is due to the fact that the chemical de-processing procedure removes BCB as well as the plastic molding compound. This paper outlines the studies carried out to determine the failure site and the root cause of the failure mechanism in a multilayer circuit and the steps taken to fix the problems. The methodology and results of this study are applicable to many other types of circuits.

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