Failure Analysis Methodology on Systematic Defect in N+ poly/NWELL Varactor in RF Analog_PLL due to Implanter Charging Issue

2012 ◽  
Author(s):  
Ang Ghim Boon ◽  
Chen Changqing ◽  
Ng Hui Peng ◽  
Neo Soh Ping ◽  
Magdeliza G ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Gate Oxide ◽  
Oxide Breakdown ◽  
Root Cause ◽  
Path Tracing ◽  
Analysis Methodology ◽  
Problem Solving Process ◽  
Access To Data ◽  
Analog Circuitry

Abstract In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

Failure Analysis Methodology on Systematic Defect in ADC_PLL Ring Pattern Due to Plasma De-Chuck Process

2010 ◽  
Author(s):  
Ang Ghim Boon ◽  
Chen Changqing ◽  
Alfred Quah ◽  
Magdeliza ◽  
Indahwan Jony ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Root Cause ◽  
Path Tracing ◽  
Analysis Methodology ◽  
Wafer Fab ◽  
Problem Solving Process

Abstract In this paper, a low yield case relating to a systematic array of failures in a ring pattern due to ADC_PLL failures on low yielding wafers will be studied. A systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current imaging, layout path tracing, PVC and XTEM together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical in a wafer foundry in which there is minimal available data on the test condition setup to duplicate the exact failure. The ring pattern was due to systematically open via as a result of polymer built-up from plasma de-chuck issue. It would serve as a good reference for a wafer Fab that encounters such an issue.

Failure Analysis Methodology on Unique 68mm Single Ring Pattern Due to Load Lock Burr

2011 ◽  
Author(s):  
A.C.T Quah ◽  
G. B. Ang ◽  
C. Q. Chen ◽  
David Zhu ◽  
M. Gunawardana ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Pattern ◽  
Root Cause ◽  
Analysis Methodology ◽  
Single Ring ◽  
Memory Failure

Abstract This paper describes a low yield case which results in a unique 68 mm single ring wafer sort failure pattern. A systematic problem solving approach with the application various FA techniques and detailed Fab investigation resolved the issue. The root cause for the unique ring failure pattern was due to a burr at the implanter load lock. The burr scratched and toppled the photoresist resulting in subsequent blocked well implantation and memory failure.

Failure Analysis Methodology on Systematic Missing Cu in RAM Due to Cu CMP

2014 ◽  
Author(s):  
Ghim Boon Ang ◽  
Changqing Chen ◽  
Hui Peng Ng ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
Removal Rate ◽  
Deep Dive ◽  
The Real ◽  
Root Cause ◽  
Analysis Methodology ◽  
Strong Emphasis ◽  
Cu Cmp

Abstract This paper places a strong emphasis on the importance of applying Systematic Problem Solving approach and use of appropriate FA methods and tools to understand the “real” failure root cause. A case of wafer center cluster RAM fail due to systematic missing Cu was studied. It was through a strong “inquisitive” mindset coupled with deep dive problem solving that lead to uncover the actual root cause of large Cu voids. The missing Cu was due to large Cu void induced by galvanic effects from the faster removal rate during Cu CMP and subsequently resulted in missing Cu. This highlights that the FA analyst’s mission is not simply to find defects but also play a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically/ physically) to Fab.

A Logical Problem Solving Process for High Via Resistance Root Cause Analysis

2008 ◽  
Author(s):  
K. Li ◽  
P. Liu ◽  
J. Teong ◽  
M. Lee ◽  
H. L. Yap
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Failure Mechanism ◽  
High Resistance ◽  
Cause Analysis ◽  
Logical Problem ◽  
Root Cause ◽  
Analysis Process ◽  
Problem Solving Process

Abstract This paper presents a case study on via high resistance issue. A logical failure analysis process EDCA (Effect, Defect, Cause, and Action) is successfully applied to find out the failure mechanism, pinpoint the root cause and solve the problem. It sets up a very good example of how to do tough failure analysis in a controllable way.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Analysis Approach on DMOS Transistor Vth Mismatch Due to Trapped Charges

2015 ◽  
Author(s):  
Hashim Ismail ◽  
Ang Chung Keow ◽  
Kenny Gan Chye Siong
Keyword(s):  
Failure Analysis ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Analysis Approach ◽  
Test Results ◽  
Root Cause ◽  
Switching Event ◽  
Output Transistor ◽  
Event Based ◽  
Trapped Charge

Abstract An output switching malfunction was reported on a bridge driver IC. The electrical verification testing revealed evidence of an earlier over current condition resulting from an abnormal voltage sense during a switching event. Based on these test results, we developed the hypothesis that a threshold voltage mismatch existed between the sense transistor and the output transistor. This paper describes the failure analysis approach we used to characterize the threshold voltage mismatch as well as our approach to determine the root cause, which was trapped charge on the gate oxide of the sense transistor.

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Device Characterization Using AFP Nanoprobing for the Localization of New Product Design Weakness

2013 ◽  
Author(s):  
Ghim Boon Ang ◽  
Alfred Quah ◽  
Changqing Chen ◽  
Si Ping Zhao ◽  
Dayanand Nagalingam ◽  
...  
Keyword(s):  
Problem Solving ◽  
Failure Analysis ◽  
Product Design ◽  
New Product ◽  
Analysis Tool ◽  
Deep Dive ◽  
Root Cause ◽  
Strong Emphasis ◽  
New Product Design ◽  
Testing Issue

Abstract This paper illustrated the beauty of AFP nano-probing as the critical failure analysis tool in localizing new product design weakness. A 40nm case of HTOL Pin Leakage due to Source/Drain punch-through at a systematic location was discussed. The root cause and mechanism was due to VDS overdrive testing issue. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.

A Comprehensive Analysis Methodology for Gate Oxide Integrity Failure Using Combined FA Techniques

2011 ◽  
Author(s):  
Hua Younan ◽  
Nistala Ramesh Rao ◽  
Chen Shuting ◽  
Zhu Lei ◽  
Chia Chin Ning ◽  
...  
Keyword(s):  
Mass Spectrometry ◽  
Detection Limit ◽  
Failure Analysis ◽  
Gate Oxide ◽  
Comprehensive Analysis ◽  
New Method ◽  
Analysis Methodology ◽  
Icp Ms ◽  
Wide Range ◽  
Gate Oxide Integrity

Abstract In this paper, a comprehensive analysis methodology for gate oxide integrity (GOI) failure using combined FA techniques is proposed. The current method integrates the failure analysis flow we previously reported with a new flow proposed in this paper. The method is applicable to a wide range of GOI failure cases and has been used in analyzing many product wafers with GOI failure. In particular, there is one wafer with GOI failure that results from known failed process machines. This wafer could be readily analyzed with this new method to identify the root causes. The newly proposed flow is based on our previous report on GOI failure analysis, but the detection limit of contamination elements was significantly improved. The enhancement of detection limit is mainly attributable to the utilization of Vapor Phase Decomposition and Inductively Coupled Plasma Mass Spectrometry (VPD ICP-MS). The ICP-MS technique is highly sensitive and capable of simultaneously measuring a large number of elements at very low concentration level in the range of ppb (part per billion) to ppt (part to trillion). This enhanced sensitivity enables effective investigation of contamination caused by specific machines. A case study of GOI failure investigated by the proposed new method will be discussed in detail. In the study, Al, Fe, Mo and Sn contamination from a suspected tool were detected by ICPMS, followed by confirmation by Secondary Ion Mass Spectrometry (SIMS) on the affected product wafers. Failurepart isolation investigations of the affected diffusion furnace revealed that the root cause of the failure is due to a defective gas flow valve.

Sign in / Sign up

Export Citation Format

Share Document