Rapid Failure Analysis of Low-Yielding Electrical Test Structures Using E-beam Physical and Voltage Contrast Inspection

2013 ◽  
Author(s):  
Oliver D. Patterson ◽  
Deborah A. Ryan ◽  
Xiaohu Tang ◽  
Shuen Cheng Lei
Keyword(s):  
Failure Analysis ◽  
Defect Detection ◽  
High Volume ◽  
The Other ◽  
Defect Inspection ◽  
Electrical Test ◽  
Detection Mode ◽  
Rapid Generation ◽  
Voltage Contrast ◽  
Additional Support

Abstract In-line E-beam inspection may be used for rapid generation of failure analysis (FA) results for low yielding test structures. This approach provides a number of advantages: 1) It is much earlier than traditional FA, 2) de-processing isn’t required, and 3) a high volume of sites can be processed with the additional support of an in-line FIB. Both physical defect detection and voltage contrast inspection modes are useful for this application. Voltage contrast mode is necessary for isolation of buried defects and is the preferred approach for opens, because it is faster. Physical defect detection mode is generally necessary to locate shorts. The considerations in applying these inspection modes for rapid failure analysis are discussed in the context of two examples: one that lends itself to physical defect inspection and the other, more appropriately addressed with voltage contrast inspection.

Methodology to Correlate Defect Reduction Systems to Electrical Test Data via Artificially Manufactured Defects

2002 ◽  
Author(s):  
Mike Santana ◽  
Alfredo V. Herrera
Keyword(s):  
Test Data ◽  
Learning Opportunities ◽  
Inspection System ◽  
Navigation Systems ◽  
Defect Inspection ◽  
Defect Reduction ◽  
Electrical Test ◽  
Important System

Abstract This paper describes a methodology for correlating physical defect inspection/navigation systems with electrical bitmap data through the fabrication of artificial defects via reticle alterations or circuit modifications using an inline FIB. The methodology chosen consisted of altering decommissioned reticles to create defects resulting in both open and shorted circuits within areas of an AMD microprocessor cache. The reticles were subsequently scanned using a KLA SL300HR StarLight inspection system to confirm their location, while wafers processed on these reticles were scanned at several layers using standard inline metrology. Finally, the wafers were electrically tested, bitmapped, and physically deprocessed. All defect data was then analyzed and cross-correlated between each system, uncovering some important system deficiencies and learning opportunities. Data and images are included to support the significance and effectiveness of such a methodology.

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

Failure Analysis and Defect Inspection of Electronic Devices by High-Resolution Cathodoluminescence

2017 ◽  
Author(s):  
C. Monachon ◽  
M.S. Zielinski ◽  
D. Gachet ◽  
S. Sonderegger ◽  
S. Muckenhirn ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Electronic Materials ◽  
Electronic Devices ◽  
Optical Emission ◽  
Large Field ◽  
Nanometer Scale ◽  
Defect Analysis ◽  
Defect Inspection ◽  
Spectrally Resolved ◽  
Non Destructive

Abstract Quantitative cathodoluminescence (CL) microscopy is a new optical spectroscopy technique that measures electron beam-induced optical emission over large field of view with a spatial resolution close to that of a scanning electron microscope (SEM). Correlation of surface morphology (SE contrast) with spectrally resolved and highly material composition sensitive CL emission opens a new pathway in non-destructive failure and defect analysis at the nanometer scale. Here we present application of a modern CL microscope in defect and homogeneity metrology, as well as failure analysis in semiconducting electronic materials

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

SRAM Failure Analysis Strategy

2003 ◽  
Author(s):  
P. Egger ◽  
C. Burmer
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
The Other ◽  
Other Hand ◽  
Analysis Strategy ◽  
Emission Microscopy ◽  
Metal Layers ◽  
Failure Localization

Abstract The area of embedded SRAMs in advanced logic ICs is increasing more and more. On the other hand smaller structure sizes and an increasing number of metal layers make conventional failure localization by using emission microscopy or liquid crystal inefficient. In this paper a SRAM failure analysis strategy will be presented independent on layout and technology.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

scholarly journals Efficient Cell Segmentation from Electroluminescent Images of Single-Crystalline Silicon Photovoltaic Modules and Cell-Based Defect Identification Using Deep Learning with Pseudo-Colorization

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4292
Author(s):  
Horng-Horng Lin ◽  
Harshad Kumar Dandage ◽  
Keh-Moh Lin ◽  
You-Teh Lin ◽  
Yeou-Jiunn Chen
Keyword(s):  
Deep Learning ◽  
Defect Detection ◽  
Crystalline Silicon ◽  
Cell Segmentation ◽  
Solar Pv ◽  
Single Crystalline Silicon ◽  
Defect Inspection ◽  
Defect Identification ◽  
Pv Modules ◽  
A Cell

Solar cells may possess defects during the manufacturing process in photovoltaic (PV) industries. To precisely evaluate the effectiveness of solar PV modules, manufacturing defects are required to be identified. Conventional defect inspection in industries mainly depends on manual defect inspection by highly skilled inspectors, which may still give inconsistent, subjective identification results. In order to automatize the visual defect inspection process, an automatic cell segmentation technique and a convolutional neural network (CNN)-based defect detection system with pseudo-colorization of defects is designed in this paper. High-resolution Electroluminescence (EL) images of single-crystalline silicon (sc-Si) solar PV modules are used in our study for the detection of defects and their quality inspection. Firstly, an automatic cell segmentation methodology is developed to extract cells from an EL image. Secondly, defect detection can be actualized by CNN-based defect detector and can be visualized with pseudo-colors. We used contour tracing to accurately localize the panel region and a probabilistic Hough transform to identify gridlines and busbars on the extracted panel region for cell segmentation. A cell-based defect identification system was developed using state-of-the-art deep learning in CNNs. The detected defects are imposed with pseudo-colors for enhancing defect visualization using K-means clustering. Our automatic cell segmentation methodology can segment cells from an EL image in about 2.71 s. The average segmentation errors along the x-direction and y-direction are only 1.6 pixels and 1.4 pixels, respectively. The defect detection approach on segmented cells achieves 99.8% accuracy. Along with defect detection, the defect regions on a cell are furnished with pseudo-colors to enhance the visualization.

Sign in / Sign up

Export Citation Format

Share Document