Failure Analysis of SRAM DQ Fault Using BIST Pattern

2018 ◽  
Author(s):  
KeonIl Kim ◽  
Yoseop Lim ◽  
GhilGeun Oh ◽  
ShinYoung Chung ◽  
Brandon Lee
Keyword(s):  
Failure Analysis ◽  
Process Improvement ◽  
Fault Location ◽  
Fault Isolation ◽  
Experimental Results ◽  
Yield Enhancement ◽  
Input Output ◽  
Isolation Technique ◽  
Innovative Method ◽  
Self Test

Abstract SRAM failure analysis (FA) provides significant value to process improvement and yield enhancement. This paper introduces an innovative method to analyze the SRAM peripheral, particularly its input/output (DQ) failures, which is not easy to isolate the fault location. In this paper, SRAM Built-In Self-Test (BIST) logic is used to generate the vectors to toggle only DQ of SRAM and an optical fault isolation technique applies to isolate the fault location. Experimental results show that the proposed method is very effective to isolate timing fault and hard defect of SRAM DQ failures.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Advanced Fault Isolation Technique Using Electro-Optical Terahertz Pulse Reflectometry (EOTPR) for 2D and 2.5D Flip-Chip Package

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Meng Yeow Tay ◽  
Wen Qiu ◽  
J. Alton ◽  
...  
Keyword(s):  
Time Domain ◽  
Flip Chip ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Experimental Results ◽  
Terahertz Pulse ◽  
Isolation And Identification ◽  
Isolation Technique ◽  
Non Destructive

Abstract Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.

Use of High Voltage OBIRCH Fault Isolation Technique in Failure Analysis of High Voltage IC's

2019 ◽  
Author(s):  
Chenran Lei ◽  
Albert Lee ◽  
Qinkan Kang ◽  
MinKwang Lee ◽  
Seiji Yang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Voltage ◽  
Fault Isolation ◽  
Isolation Technique

Verification of DLS Data by LVP in Case of Marginal Failure

2016 ◽  
Author(s):  
Keonil Kim ◽  
Sungjin Kim ◽  
Kunjae Lee ◽  
Kyeongju Jin ◽  
Yunwoo Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Fault Location ◽  
Photon Emission ◽  
Fault Localization ◽  
Fault Isolation ◽  
The Real ◽  
Defect Isolation ◽  
The Relationship ◽  
Non Destructive

Abstract In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

Multi-Level Approach for High-Precision Cache Fault Isolation—Case Study: Itanium® II Processor Low Voltage Cache Yield Improvement

2004 ◽  
Author(s):  
Chia Ling Kong ◽  
Mohammed R. Islam
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Low Voltage ◽  
Circuit Simulation ◽  
Physical Structure ◽  
Fault Isolation ◽  
Embedded Memory ◽  
Yield Improvement ◽  
Multi Level

Abstract Fault Isolation / Failure Analysis (FI/FA) of increasingly complex embedded memory in microprocessors is becoming more difficult due to process scaling and presence of subtle defects. As physical failure analysis (PFA) is destructive and involves expensive and time-consuming processes, fault diagnosis needs to be as precise as possible to ensure successful physical defect sighting. This paper introduces a cache Fault Isolation methodology that focuses on exhaustive data collection to derive concrete hypothesis of physical fault location and to overcome the existing FA/FI challenges. The methodology involves a novel application of existing DFT techniques in combination with circuit analysis, pattern hacking, defect localization and PFA tools. Some of the techniques, for example pattern modification or circuit simulation, are applied repeatedly in order to obtain higher-level of isolation – from cell/logic level to transistor/gate level, and finally down to physical structure/layer level. This multi-level FI approach is the key to localize the failing area to greater precision, which had proven itself in Intel Itanium® II processor yield improvement process.

Identification of Defective Fin by E-beam Induced Current in Advanced FinFET Device Failure Analysis

2018 ◽  
Author(s):  
Yuting Wei ◽  
Chuan Zhang ◽  
Liangshan Chen ◽  
Oh Chong Khiam
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Induced Current ◽  
Large Area ◽  
Mos Capacitor ◽  
Isolation Technique ◽  
Root Cause ◽  
Area Of Interest ◽  
First Case ◽  
Line Test

Abstract E-beam induced current technique is a fault isolation technique based on SEM-based nanoprobers. Electron beam induced current (EBIC) can help failure analysts quickly identify the defective device with abnormal junction behavior from a relatively large area of interest. Using EBIC, defects can be pin-pointed down to individual Fin, which significantly enhanced the success rate. In this paper, two cases are used as examples to illustrate how this failure analysis (FA) methodology provides a powerful and efficient solution in localizing defective fins. In the first case, a local full bit-line fail was submitted for failure analysis. In the second case, a MOS capacitor parametric test structure designed to monitor gate oxide break down voltage that showed early break down behavior during in-line test. Failure analysis was requested to investigate the root-cause.

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