Identification of Defective Fin by E-beam Induced Current in Advanced FinFET Device Failure Analysis

2018 ◽  
Author(s):  
Yuting Wei ◽  
Chuan Zhang ◽  
Liangshan Chen ◽  
Oh Chong Khiam
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Induced Current ◽  
Large Area ◽  
Mos Capacitor ◽  
Isolation Technique ◽  
Root Cause ◽  
Area Of Interest ◽  
First Case ◽  
Line Test

Abstract E-beam induced current technique is a fault isolation technique based on SEM-based nanoprobers. Electron beam induced current (EBIC) can help failure analysts quickly identify the defective device with abnormal junction behavior from a relatively large area of interest. Using EBIC, defects can be pin-pointed down to individual Fin, which significantly enhanced the success rate. In this paper, two cases are used as examples to illustrate how this failure analysis (FA) methodology provides a powerful and efficient solution in localizing defective fins. In the first case, a local full bit-line fail was submitted for failure analysis. In the second case, a MOS capacitor parametric test structure designed to monitor gate oxide break down voltage that showed early break down behavior during in-line test. Failure analysis was requested to investigate the root-cause.

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Failure Analysis From Back Side of Die

1996 ◽  
Author(s):  
N.M. Wu ◽  
K. Weaver ◽  
J.H. Lin
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Back Side ◽  
Induced Current ◽  
Front Side ◽  
Root Cause ◽  
Isolation Techniques ◽  
Cause Of Failure ◽  
Emission Microscopy ◽  
Side Emission

Abstract With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Time Domain Reflectometry Technique for Failure Analysis

2004 ◽  
Author(s):  
Teoh King Long ◽  
Ko Yin Fern
Keyword(s):  
Failure Analysis ◽  
Time Domain ◽  
Time Domain Reflectometry ◽  
Fault Isolation ◽  
Reference Plane ◽  
First Case ◽  
Main Emphasis ◽  
Plastic Ball ◽  
Solder Balls ◽  
Non Destructive

Abstract In time domain reflectometry (TDR), the main emphasis lies on the reflected waveform. Poor probing contact is one of the common problems in getting an accurate waveform. TDR probe normalization is essential before measuring any TDR waveforms. The advantages of normalization include removal of test setup errors in the original test pulse and the establishment of a measurement reference plane. This article presents two case histories. The first case is about a Plastic Ball Grid Array package consisting of 352 solder balls where the open failure mode was encountered at various terminals after reliability assessment. In the second, a three-digit display LED suspected of an electrical short failure was analyzed using TDR as a fault isolation tool. TDR has been successfully used to perform non-destructive fault isolation in assisting the routine failure analysis of open and short failure. It is shown to be accurate and reduces the time needed to identify fault locations.

Use of High Voltage OBIRCH Fault Isolation Technique in Failure Analysis of High Voltage IC's

2019 ◽  
Author(s):  
Chenran Lei ◽  
Albert Lee ◽  
Qinkan Kang ◽  
MinKwang Lee ◽  
Seiji Yang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Voltage ◽  
Fault Isolation ◽  
Isolation Technique

Application of Focused Ion Beam System as A Defect Localization and Root Cause Analysis Tool

2001 ◽  
Author(s):  
C.C. Ooi ◽  
K.H. Siek ◽  
K.S. Sim
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Analysis Tool ◽  
Root Cause ◽  
Beam System ◽  
Defect Localization ◽  
Challenging Environment ◽  
Microprocessor Technology

Abstract Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

Challenges of System Level Failure Analysis of Electronics in the Automotive Industry

2017 ◽  
Author(s):  
Bence Hevesi
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Automotive Industry ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
System Level ◽  
Cause Analysis ◽  
Root Cause ◽  
Analysis Workflow

Abstract In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

Failure Analysis Work Flow for Electrical Shorts in Triple Stacked 3D TSV Daisy Chains

2015 ◽  
Vol 2015 (1) ◽  
pp. 000469-000473 ◽  
Author(s):  
J. Gaudestad ◽  
A. Orozco ◽  
I. De Wolf ◽  
T. Wang ◽  
T. Webers ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Root Cause ◽  
Current Path ◽  
Dual Beam ◽  
Resolution Imaging ◽  
Magnetic Field Imaging ◽  
Non Destructive

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

Targeted Silicon Ultra-Thinning by Contour Milling for Advanced Fault Isolation

2019 ◽  
Author(s):  
W. S. Teo ◽  
M.S. Wei ◽  
V. Narang ◽  
C. L. Gan ◽  
C. Richardson ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Thin Sample ◽  
Electrical Failure ◽  
Contour Maps ◽  
Area Of Interest ◽  
Silicon Thickness ◽  
Thermal Stability Of

Abstract In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.

A Novel Fault Isolation Technique for Identifying Deep Sub-Micron Defects

2003 ◽  
Author(s):  
Fayik M. Bundhoo ◽  
Soundaranathan Kasivisvanatha
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Side Wall ◽  
Fault Isolation ◽  
Crystalline Lattice ◽  
Isolation Technique ◽  
Silicon Lattice ◽  
Root Cause ◽  
Wet Chemical ◽  
Metal Layers

Abstract A novel failure analysis approach has been developed to isolate and characterize deep sub micron defects in P<100>- silicon lattice. This technique utilizes unique wet chemical deprocessing and side wall cleaning in conjunction with focused ion beam milling to isolate a single vertical failing DMOS source contact from a parallel array of 462K contacts covered with oxide dielectric and top metal layers. The two methods of analysis and root cause of crystalline lattice dislocation in a vertical DMOS transistor are discussed. TEM examination of implanted dopant interface was carried out in order to determine the nature and origin of lattice dislocations. A study1 indicates that lattice dislocations are generated by deep boron and arsenic implants that are not adequately annealed. In our analysis, these dislocations were observed as loop pairs causing low-level leakage that did not initially allow the part to fail. However, these silicon lattice dislocations do pose reliability issues.

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