scholarly journals The Cost of Energy-Efficiency in Digital Hardware: The Trade-Off between Energy Dissipation, Energy–Delay Product and Reliability in Electronic, Magnetic and Optical Binary Switches

2021 ◽  
Vol 11 (12) ◽  
pp. 5590
Author(s):  
Rahnuma Rahman ◽  
Supriyo Bandyopadhyay
Keyword(s):  
Energy Dissipation ◽  
Error Probability ◽  
Optical Switch ◽  
Magnetic Tunnel Junction ◽  
Spin Transfer Torque ◽  
Oxide Semiconductor ◽  
Dissipation Energy ◽  
Trade Off ◽  
The Cost ◽  
Energy Delay Product

Binary switches, which are the primitive units of all digital computing and information processing hardware, are usually benchmarked on the basis of their ‘energy–delay product’, which is the product of the energy dissipated in completing the switching action and the time it takes to complete that action. The lower the energy–delay product, the better the switch (supposedly). This approach ignores the fact that lower energy dissipation and faster switching usually come at the cost of poorer reliability (i.e., a higher switching error rate) and hence the energy–delay product alone cannot be a good metric for benchmarking switches. Here, we show the trade-off between energy dissipation, energy–delay product and error–probability for an electronic switch (a metal oxide semiconductor field effect transistor), a magnetic switch (a magnetic tunnel junction switched with spin transfer torque) and an optical switch (bistable non-linear mirror). As expected, reducing energy dissipation and/or energy–delay product generally results in increased switching error probability and reduced reliability.

scholarly journals The Cost of Energy-Efficiency in Digital Hardware: The Trade-off between Energy Dissipation, Energy-Delay Product and Reliability in Electronic and Magnetic Binary Switches

2021 ◽  
Author(s):  
Rahnuma Rahman ◽  
Supriyo Bandyopadhyay
Keyword(s):  
Energy Dissipation ◽  
Error Probability ◽  
Magnetic Tunnel Junction ◽  
Spin Transfer Torque ◽  
Oxide Semiconductor ◽  
Dissipation Energy ◽  
Trade Off ◽  
Cost Of Energy ◽  
The Cost ◽  
Energy Delay Product

Binary switches, which are the primitive units of all digital computing and information processing hardware, are usually benchmarked on the basis of their ‘energy-delay product’ which is the product of the energy dissipated in completing the switching action and the time it takes to complete that action. The lower the energy-delay product, the better the switch (supposedly). This approach ignores the fact that lower energy dissipation and faster switching usually come at the cost of poorer reliability (i. e. higher switching error rate) and hence the energy-delay product alone cannot be a good metric for benchmarking switches. Here, we show the trade-off between energy dissipation, energy-delay product and error-probability, for both an electronic switch (a metal oxide semiconductor field effect transistor) and a magnetic switch (a magnetic tunnel junction switched with spin transfer torque). As expected, reducing energy dissipation and/or energy-delay-product generally results in increased switching error probability and reduced reliability.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates

2013 ◽  
Vol 854 ◽  
pp. 89-95 ◽  
Author(s):  
Hiwa Mahmoudi ◽  
T. Windbacher ◽  
V. Sverdlov ◽  
S. Selberherr
Keyword(s):  
Tunnel Junction ◽  
Error Probability ◽  
Magnetic Tunnel Junction ◽  
Logic Gates ◽  
Optimization Method ◽  
Spin Transfer Torque ◽  
Boolean Logic ◽  
Stability Factor ◽  
Gate Circuit ◽  
Reliability Based Optimization

Recently, magnetic tunnel junction (MTJ)-based implication logic gates have been proposed to realize a fundamental Boolean logic operation called material implication (IMP). For given MTJ characteristics, the IMP gate circuit parameters must be optimized to obtain the minimum IMP error probability. In this work we present the optimization method and investigate the effect of MTJ device parameters on the reliability of IMP logic gates. It is shown that the most important MTJ device parameters are the tunnel magnetoresistance (TMR) ratio and the thermal stability factor Δ. The IMP error probability decreases exponentially with increasing TMR and Δ.

scholarly journals Design and analysis of SHE-assisted STT MTJ/CMOS logic gates

2021 ◽  
Author(s):  
Prashanth Barla ◽  
Vinod Kumar Joshi ◽  
Somashekara Bhat
Keyword(s):  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Orbit Interaction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Oxide Semiconductor ◽  
Metal Materials ◽  
Power Delay Product

AbstractWe have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.

Developing Schedule With Linear Programming (Case Study: STTF II Project Komplek Sukamukti Banjaran)

2020 ◽  
Vol 4 (02) ◽  
pp. 34-45
Author(s):  
Naufal Dzikri Afifi ◽  
Ika Arum Puspita ◽  
Mohammad Deni Akbar
Keyword(s):  
Linear Programming ◽  
Objective Function ◽  
Project Scheduling ◽  
Time Limit ◽  
Minimum Time ◽  
Service Cost ◽  
Trade Off ◽  
Overtime Work ◽  
The Cost

Shift to The Front II Komplek Sukamukti Banjaran Project is one of the projects implemented by one of the companies engaged in telecommunications. In its implementation, each project including Shift to The Front II Komplek Sukamukti Banjaran has a time limit specified in the contract. Project scheduling is an important role in predicting both the cost and time in a project. Every project should be able to complete the project before or just in the time specified in the contract. Delay in a project can be anticipated by accelerating the duration of completion by using the crashing method with the application of linear programming. Linear programming will help iteration in the calculation of crashing because if linear programming not used, iteration will be repeated. The objective function in this scheduling is to minimize the cost. This study aims to find a trade-off between the costs and the minimum time expected to complete this project. The acceleration of the duration of this study was carried out using the addition of 4 hours of overtime work, 3 hours of overtime work, 2 hours of overtime work, and 1 hour of overtime work. The normal time for this project is 35 days with a service fee of Rp. 52,335,690. From the results of the crashing analysis, the alternative chosen is to add 1 hour of overtime to 34 days with a total service cost of Rp. 52,375,492. This acceleration will affect the entire project because there are 33 different locations worked on Shift to The Front II and if all these locations can be accelerated then the duration of completion of the entire project will be effective

scholarly journals Black Hole Algorithm for Sustainable Design of Counterfort Retaining Walls

2020 ◽  
Vol 12 (7) ◽  
pp. 2767 ◽  
Author(s):  
Víctor Yepes ◽  
José V. Martí ◽  
José García
Keyword(s):  
Black Hole ◽  
Sustainable Design ◽  
Retaining Walls ◽  
The Other ◽  
Trade Off ◽  
Construction Company ◽  
Geometric Variables ◽  
The Stability ◽  
The Cost ◽  
Black Hole Algorithm

The optimization of the cost and CO 2 emissions in earth-retaining walls is of relevance, since these structures are often used in civil engineering. The optimization of costs is essential for the competitiveness of the construction company, and the optimization of emissions is relevant in the environmental impact of construction. To address the optimization, black hole metaheuristics were used, along with a discretization mechanism based on min–max normalization. The stability of the algorithm was evaluated with respect to the solutions obtained; the steel and concrete values obtained in both optimizations were analyzed. Additionally, the geometric variables of the structure were compared. Finally, the results obtained were compared with another algorithm that solved the problem. The results show that there is a trade-off between the use of steel and concrete. The solutions that minimize CO 2 emissions prefer the use of concrete instead of those that optimize the cost. On the other hand, when comparing the geometric variables, it is seen that most remain similar in both optimizations except for the distance between buttresses. When comparing with another algorithm, the results show a good performance in optimization using the black hole algorithm.

Hybrid last mile delivery fleets with crowdsourcing: A systems view of managing the cost‐service trade‐off

2021 ◽  
Author(s):  
Vincent E. Castillo ◽  
John E. Bell ◽  
Diane A. Mollenkopf ◽  
Theodore P. Stank
Keyword(s):  
Service Trade ◽  
Trade Off ◽  
Last Mile ◽  
The Cost ◽  
Last Mile Delivery ◽  
Systems View

scholarly journals Aggregation of cohorts for histopathological diagnosis with deep morphological analysis

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Jeonghyuk Park ◽  
Yul Ri Chung ◽  
Seo Taek Kong ◽  
Yeong Won Kim ◽  
Hyunho Park ◽  
...  
Keyword(s):  
Cancer Detection ◽  
Morphological Analysis ◽  
Deep Neural Networks ◽  
Large Datasets ◽  
Histopathological Diagnosis ◽  
Single Model ◽  
Trade Off ◽  
Detection Model ◽  
Optimal Behavior ◽  
The Cost

AbstractThere have been substantial efforts in using deep learning (DL) to diagnose cancer from digital images of pathology slides. Existing algorithms typically operate by training deep neural networks either specialized in specific cohorts or an aggregate of all cohorts when there are only a few images available for the target cohort. A trade-off between decreasing the number of models and their cancer detection performance was evident in our experiments with The Cancer Genomic Atlas dataset, with the former approach achieving higher performance at the cost of having to acquire large datasets from the cohort of interest. Constructing annotated datasets for individual cohorts is extremely time-consuming, with the acquisition cost of such datasets growing linearly with the number of cohorts. Another issue associated with developing cohort-specific models is the difficulty of maintenance: all cohort-specific models may need to be adjusted when a new DL algorithm is to be used, where training even a single model may require a non-negligible amount of computation, or when more data is added to some cohorts. In resolving the sub-optimal behavior of a universal cancer detection model trained on an aggregate of cohorts, we investigated how cohorts can be grouped to augment a dataset without increasing the number of models linearly with the number of cohorts. This study introduces several metrics which measure the morphological similarities between cohort pairs and demonstrates how the metrics can be used to control the trade-off between performance and the number of models.

scholarly journals A trade-off between classical and quantum circuit size for an attack against CSIDH

2020 ◽  
Vol 15 (1) ◽  
pp. 4-17
Author(s):  
Jean-François Biasse ◽  
Xavier Bonnetain ◽  
Benjamin Pring ◽  
André Schrottenloher ◽  
William Youmans
Keyword(s):  
Endomorphism Ring ◽  
State Of The Art ◽  
Quantum Circuit ◽  
List Type ◽  
Hard Problem ◽  
Trade Off ◽  
Classical State ◽  
Security Parameter ◽  
The Cost ◽  
Quadratic Order

AbstractWe propose a heuristic algorithm to solve the underlying hard problem of the CSIDH cryptosystem (and other isogeny-based cryptosystems using elliptic curves with endomorphism ring isomorphic to an imaginary quadratic order 𝒪). Let Δ = Disc(𝒪) (in CSIDH, Δ = −4p for p the security parameter). Let 0 < α < 1/2, our algorithm requires:A classical circuit of size $2^{\tilde{O}\left(\log(|\Delta|)^{1-\alpha}\right)}.$A quantum circuit of size $2^{\tilde{O}\left(\log(|\Delta|)^{\alpha}\right)}.$Polynomial classical and quantum memory.Essentially, we propose to reduce the size of the quantum circuit below the state-of-the-art complexity $2^{\tilde{O}\left(\log(|\Delta|)^{1/2}\right)}$ at the cost of increasing the classical circuit-size required. The required classical circuit remains subexponential, which is a superpolynomial improvement over the classical state-of-the-art exponential solutions to these problems. Our method requires polynomial memory, both classical and quantum.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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