Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

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Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2020.2727 ◽

2020 ◽

Vol 15 (1) ◽

pp. 142-146

Author(s):

Liang Dai ◽

Wei-Feng Lü

Keyword(s):

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistors ◽

Line Edge Roughness ◽

Metal Gate ◽

Edge Roughness ◽

Simulation Results ◽

Dual Metal ◽

Aided Design ◽

First Time

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

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Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

Applied Sciences ◽

10.3390/app10248880 ◽

2020 ◽

Vol 10 (24) ◽

pp. 8880

Author(s):

Min Woo Kang ◽

Woo Young Choi

Keyword(s):

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistors ◽

Three Dimensional ◽

Gate Insulator ◽

Radius Of Curvature ◽

Computer Aided ◽

Simulation Results ◽

Tcad Simulation ◽

Aided Design

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

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Study of Work-Function Variation on Performance of Dual-Metal Gate Fin Field-Effect Transistor

Machine Learning and Artificial Intelligence - Frontiers in Artificial Intelligence and Applications ◽

10.3233/faia200805 ◽

2020 ◽

Author(s):

Tianyu Yu ◽

Liang Dai ◽

Zhifeng Zhao ◽

Weifeng Lyu ◽

Mi Lin

Keyword(s):

Work Function ◽

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistor ◽

Metal Gate ◽

Statistical Fluctuations ◽

Effect Transistor ◽

Dual Metal ◽

Aided Design ◽

The Impact

The impact of work-function variation (WFV) on performance of an inversion-mode (IM) dual-metal gate (DMG) fin field-effect transistor (FinFET) was investigated for the first time. The statistical fluctuations induced by WFV on the threshold-voltage (VTH), transconductance (gm), and subthreshold slope (SS) were demonstrated and estimated utilizing a 3D technology computer-aided design (TCAD) simulator. We found that the performance variations of the DMG FinFET were affected by two different metals near the drain and near the source, respectively. Additionally, this effect of the two metals on the channel was not monotonic with the length of the channel of their own control. Our work fills a gap in the study of WFV for a DMG IM FinFET and provides a reference for optimizing the distribution of the two metals.

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Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

Japanese Journal of Applied Physics ◽

10.7567/jjap.52.04cc01 ◽

2013 ◽

Vol 52 (4S) ◽

pp. 04CC01 ◽

Cited By ~ 2

Author(s):

Geert Eneman ◽

An De Keersgieter ◽

Liesbeth Witters ◽

Jerome Mitard ◽

Benjamin Vincent ◽

...

Keyword(s):

Computer Aided Design ◽

Field Effect ◽

Field Effect Transistors ◽

Design Study ◽

Computer Aided ◽

P Type ◽

Aided Design

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Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽

10.3390/electronics10040454 ◽

2021 ◽

Vol 10 (4) ◽

pp. 454

Author(s):

You Wang ◽

Yu Mao ◽

Qizheng Ji ◽

Ming Yang ◽

Zhaonian Yang ◽

...

Keyword(s):

Integrated Circuits ◽

Computer Aided Design ◽

Field Effect ◽

Electrostatic Discharge ◽

Field Effect Transistors ◽

Test Method ◽

Current Path ◽

Simulation Results ◽

Current Characteristics ◽

Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

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