scholarly journals Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

2020 ◽  
Vol 10 (24) ◽  
pp. 8880
Author(s):  
Min Woo Kang ◽  
Woo Young Choi
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Gate Insulator ◽  
Radius Of Curvature ◽  
Computer Aided ◽  
Simulation Results ◽  
Tcad Simulation ◽  
Aided Design

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

scholarly journals Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 282 ◽  
Author(s):  
Liang Dai ◽  
Weifeng Lü ◽  
Mi Lin
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Voltage ◽  
Metal Gate ◽  
Random Dopant Fluctuation ◽  
Computer Aided ◽  
Dual Metal ◽  
Aided Design ◽  
Random Dopant

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Impact of Pulse Quenching Effect on Sensitive Area at Advanced Technologies

2013 ◽  
Vol 392 ◽  
pp. 693-696
Author(s):  
Wen Tao Xu ◽  
Yang Guo ◽  
Yan Kang Du
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Sensitive Area ◽  
Isolation Technique ◽  
Quenching Effect ◽  
Advanced Technologies ◽  
Computer Aided ◽  
Simulation Results ◽  
Aided Design ◽  
The Impact

The impact of pulse quenching effect on the sensitive area is evaluated by using three-dimensional technology computer-aided design (TCAD) numerical simulation. Simulation results present that the pulse quenching effect could effectively reduce the sensitive area of PMOS transistors. By adopting the off-state gate isolation technique, the sensitive area is further reduced.

Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

2013 ◽  
Vol 52 (4S) ◽  
pp. 04CC01 ◽  
Author(s):  
Geert Eneman ◽  
An De Keersgieter ◽  
Liesbeth Witters ◽  
Jerome Mitard ◽  
Benjamin Vincent ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Design Study ◽  
Computer Aided ◽  
P Type ◽  
Aided Design

Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors

2020 ◽  
Vol 15 (1) ◽  
pp. 142-146
Author(s):  
Liang Dai ◽  
Wei-Feng Lü
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Line Edge Roughness ◽  
Metal Gate ◽  
Edge Roughness ◽  
Simulation Results ◽  
Dual Metal ◽  
Aided Design ◽  
First Time

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

scholarly journals The Analysis of SEU in Nanowire FETs and Nanosheet FETs

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 863
Author(s):  
Yunjae Kim ◽  
Myounggon Kang
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Incident Angle ◽  
Three Dimensional ◽  
Design Tools ◽  
Single Event Upset ◽  
Single Event ◽  
The Difference ◽  
Aided Design

The effects of the single-event upset (SEU) generated by radiation on nanowire field-effect transistors (NW-FETs) and nanosheet (NS)-FETs were analyzed according to the incident angle and location of radiation, by using three-dimensional technology computer-aided design tools. The greatest SEU occurred when the particle was incident at 90°, whereas the least occurred at 15°. SEU was significantly affected when the particle was incident on the drain, as compared to when it was incident on the source. The NS-FETs were robust to SEU, unlike the NW-FETs. This phenomenon can be attributed to the difference in the area exposed to radiation, even if the channel widths of these devices were identical.

scholarly journals Automatized Evaluation of Students’ CAD Models

2021 ◽  
Vol 11 (4) ◽  
pp. 145
Author(s):  
Nenad Bojcetic ◽  
Filip Valjak ◽  
Dragan Zezelj ◽  
Tomislav Martinec
Keyword(s):  
Computer Aided Design ◽  
Three Dimensional ◽  
Computer Application ◽  
Test Cases ◽  
Cad Model ◽  
Computer Solution ◽  
3D Cad ◽  
Computer Aided ◽  
Cad Models ◽  
Aided Design

The article describes an attempt to address the automatized evaluation of student three-dimensional (3D) computer-aided design (CAD) models. The driving idea was conceptualized under the restraints of the COVID pandemic, driven by the problem of evaluating a large number of student 3D CAD models. The described computer solution can be implemented using any CAD computer application that supports customization. Test cases showed that the proposed solution was valid and could be used to evaluate many students’ 3D CAD models. The computer solution can also be used to help students to better understand how to create a 3D CAD model, thereby complying with the requirements of particular teachers.

Determination of the Workspace of a Three-Degrees-of-Freedom Parallel Manipulator Using a Three-Dimensional Computer-Aided-Design Software Package and the Concept of Virtual Chains1

2015 ◽  
Vol 8 (2) ◽  
Author(s):  
Andrew Johnson ◽  
Xianwen Kong ◽  
James Ritchie
Keyword(s):  
Computer Aided Design ◽  
Parallel Manipulator ◽  
Degrees Of Freedom ◽  
Graphical Representation ◽  
Three Dimensional ◽  
Parallel Manipulators ◽  
Workspace Analysis ◽  
Computer Aided ◽  
Aided Design

The determination of workspace is an essential step in the development of parallel manipulators. By extending the virtual-chain (VC) approach to the type synthesis of parallel manipulators, this technical brief proposes a VC approach to the workspace analysis of parallel manipulators. This method is first outlined before being illustrated by the production of a three-dimensional (3D) computer-aided-design (CAD) model of a 3-RPS parallel manipulator and evaluating it for the workspace of the manipulator. Here, R, P and S denote revolute, prismatic and spherical joints respectively. The VC represents the motion capability of moving platform of a manipulator and is shown to be very useful in the production of a graphical representation of the workspace. Using this approach, the link interferences and certain transmission indices can be easily taken into consideration in determining the workspace of a parallel manipulator.

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