scholarly journals Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 496 ◽  
Author(s):  
Muhammad Shakir ◽  
Shuoben Hou ◽  
Raheleh Hedayati ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Large Scale ◽  
Extreme Environment ◽  
Design Criterion ◽  
Vlsi Circuits ◽  
Design Flow ◽  
Collector Current ◽  
Threshold Voltage Shift ◽  
Flip Flop

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

Skill Needs in VLSI Circuits

1992 ◽  
Vol 6 (1) ◽  
pp. 50-50
Author(s):  
Klaus Wölcken
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Design ◽  
Vlsi Circuits ◽  
Academic Institutions ◽  
Directorate General

The forecast need for designers of Very Large Scale Integrated Circuits is described. The article then goes on to outline the support being provided for academic institutions involved with VLSI design training by the European Commission's Directorate General XIII.

Digital and Analogue Integrated Circuits in Silicon Carbide for High Temperature Operation

2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000373-000377 ◽  
Author(s):  
E.P Ramsay ◽  
D.T. Clark ◽  
J.D. Cormack ◽  
A.E. Murphy ◽  
D.A Smith ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Nand Gate ◽  
Cmos Process ◽  
Flip Flop ◽  
Aero Engines ◽  
Simple Logic ◽  
High Temperature Operation

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.

Contact Resistance and Methods for its Determination

1982 ◽  
Vol 18 ◽  
Author(s):  
S. Simon Cohen
Keyword(s):  
Integrated Circuits ◽  
Contact Resistance ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Vlsi Circuits ◽  
Single Element ◽  
Large Scale Integration ◽  
Proper Definition ◽  
Definition Of ◽  
Scale Integration

The problem of low resistance ohmic contacts to silicon has been of considerable technological interest. In recent years this problem has received special attention owing to the effect of scaling in very-large-scale integration (VLSI) technology. The field of ohmic contacts to semiconductors comprises two independent parts. First there exists the material science aspect. The choice of a suitable metallization system, the proper semiconductor parameters and the method of the contact formation is not obvious. Then there is the question of the proper definition of the contact resistance and the way it is measured.Several methods for contact resistance determination have been introduced in the past. All seem to have some drawbacks that either limit their usefulness or raise doubts as to their validity in certain situations. We shall discuss the two-, three- and four-terminal resistor methods of measurement. Relevant theoretical considerations will also be included.For conventional integrated circuits with a moderate junction depth of 1–2 μm, aluminum is uniquely suited as a single-element metallization system. However, for VLSI applications it may become obsolete because of several well-defined metallurgical problems. Thus, other metallization systems have to be investigated. We shall briefly discuss some recent data on several other metallization systems. Finally, the problem of size effects on the contact resistance will be discussed. Recent experimental results suggest important clues regarding the development of alternative metallization systems for VLSI circuits and also point to revisions of estimates of achievable design rules.

Digital Logic Synthesis for 470 Celsius Silicon Carbide Electronics

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000064-000070
Author(s):  
N. Chiolino ◽  
A. M. Francis ◽  
J. Holmes ◽  
M. Barlow
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuit ◽  
Computer Aided Design ◽  
Large Scale ◽  
Logic Synthesis ◽  
Digital Design ◽  
Design Flow ◽  
Cmos Process ◽  
Cell Placement

Abstract Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.

scholarly journals Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

2017 ◽  
Author(s):  
Vinícius Dos Santos Livramento ◽  
José Luís Güntzel
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Consumer Electronics ◽  
Clock Frequency ◽  
Wide Range ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

Metallization for Very-Large-Scale Integrated Circuits

1981 ◽  
Vol 10 ◽  
Author(s):  
P. B. Ghate
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Vlsi Circuit ◽  
Chip Area ◽  
Circuit Performance ◽  
Platinum Silicide ◽  
Silicon Crystals ◽  
Device Structures

Progress in patterning technologies and computer-aided circuit designs have brought us to the threshold of very-large-scale integrated (VLSI) circuits with 100 000 or more devices to be integrated on a silicon chip. In this paper we review thin film applications in the fabrication of contacts and interconnects for VLSI circuits. Device structures suitable for both bipolar and metal/oxide/semiconductor (MOS) VLSI circuit applications tend to have shallow junction depths and contact areas (silicon-metal interfaces) in the 0.2–0.5 μm and 1–2μm2 ranges respectively; also some of the circuits require Schottky barrier diodes. Consumption of silicon in the contact windows needs to be minimized with the use of silicide layers for siliconmetal contacts. The formation and use of platinum silicide layers for bipolar applications are reviewed. Our observations indicate that the carbon and oxygen present in Czochralski-grown silicon crystals interfere in platinum silicide formationand affect the electrical characteristics of the contacts. The use of barrier layers in VLSI metallization is illustrated. The interdependence of film microstructure, electromigration-induced failures and VLSI interconnection reliability is examined. The integration of a large number of components on a VLSI chip with a single level of interconnections consumes more chip area. Long interconnection paths adversely affect circuit performance. Multilevel interconnections (conductor/insulator/conductor) offer an attractive solution to increase the packing density and circuit performance. The application of PtSi/(Ti: W)/(Al-Cu)/SiO2 /(Ti: W)/A1 film layers in the fabrication of a bipolar VLSI circuit with a minimum feature size of 1.25 μm is illustrated. As the complexity of VLSI circuits continues to grow with micron size device structures, three or more levels of interconnections compatible with shallow junctions on the substrates and complex packaging technologies are required. Areas of concern and desirable features in VLSI metallization are summarized.

A Model Study of Thermal Stress-Induced Voiding in Electronic Packages

1996 ◽  
Vol 118 (4) ◽  
pp. 229-234 ◽  
Author(s):  
Y. Huang ◽  
K. X. Hu ◽  
C. P. Yeh ◽  
N.-Y. Li ◽  
K. C. Hwang
Keyword(s):  
Integrated Circuits ◽  
Stress Level ◽  
Large Scale ◽  
Volume Fraction ◽  
Design Criterion ◽  
Mean Stress ◽  
Electronic Packages ◽  
Conductive Adhesives ◽  
Perfectly Plastic ◽  
Cavitation Instability

Thin film metallizations are one of the most important interconnects in large-scale integrated circuits. They are covered by substrates and passivation films. Large hydrostatic (mean) tension develops due to the constraint and thermal mismatch, and voiding is identified as the failure mechanism. This phenomenon of rapid nucleation and growth of voids is called cavitation instability and it can lead to the failure of ductile components in electronic packages such as metallizations. A micromechanics model is developed to provide the critical mean stress level that will trigger the cavitation instability. It is found that this critical mean stress level the cavitation stress, not only depends on the material properties but also is very sensitive to defects in the material. For example, the cavitation stress decreases drastically as the void volume fraction increases. The stress-based design criterion for ductile components in electronic packages should then be: (1) Von Mises effective stress < yield stress; and (2) mean stress < cavitation stress, which is particularly important to the constrained ductile components in electronic packages such as vias and conductive adhesives. An analytical expression of cavitation stress for elastic-perfectly plastic solids is obtained, and numerical results for elastic-power law hardening solids are presented.

scholarly journals Selective Flip-Flop Optimization for Circuit Reliability

2020 ◽  
pp. 337-364
Author(s):  
Mohammad Saber Golanbari ◽  
Mojtaba Ebrahimi ◽  
Saman Kiamehr ◽  
Mehdi B. Tahoori
Keyword(s):  
Large Scale ◽  
Supply Voltage ◽  
Voltage Drop ◽  
Vlsi Circuits ◽  
Optimization Approach ◽  
Voltage Fluctuation ◽  
Flip Flop ◽  
Bias Temperature Instability ◽  
Optimization Methodology ◽  
Critical Components

AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.

Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

2021 ◽  
Vol 2021 (HiTEC) ◽  
pp. 000118-000122
Author(s):  
S. Perez ◽  
A.M. Francis ◽  
J. Holmes ◽  
T. Vrotsos
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Extreme Environment ◽  
Integrated Circuit Design ◽  
Device Model ◽  
Effect Transistor ◽  
R Process

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

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