Selective Flip-Flop Optimization for Circuit Reliability

AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.

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Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2021.2984 ◽

2021 ◽

Vol 16 (4) ◽

pp. 602-611

Author(s):

A. N. Duraivel ◽

B. Paulchamy ◽

K. Mahendrakan

Keyword(s):

High Performance ◽

Large Scale ◽

Supply Voltage ◽

Clock Cycle ◽

The State ◽

High Threshold ◽

Clock Signal ◽

Signal Transfer ◽

Flip Flop ◽

Sleep Transistors

Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.

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Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications

Electronics ◽

10.3390/electronics8050496 ◽

2019 ◽

Vol 8 (5) ◽

pp. 496 ◽

Cited By ~ 3

Author(s):

Muhammad Shakir ◽

Shuoben Hou ◽

Raheleh Hedayati ◽

Bengt Gunnar Malm ◽

Mikael Östling ◽

...

Keyword(s):

Silicon Carbide ◽

Integrated Circuits ◽

Large Scale ◽

Extreme Environment ◽

Design Criterion ◽

Vlsi Circuits ◽

Design Flow ◽

Collector Current ◽

Threshold Voltage Shift ◽

Flip Flop

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

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High Stable and Low Power 10T CNTFET SRAM Cell

Journal of Circuits System and Computers ◽

10.1142/s0218126620501583 ◽

2019 ◽

Vol 29 (10) ◽

pp. 2050158

Author(s):

M. Elangovan ◽

K. Gunavathi

Keyword(s):

Power Consumption ◽

Low Power ◽

Large Scale ◽

Supply Voltage ◽

Memory Cell ◽

Vlsi Circuits ◽

Order Effects ◽

Power Performance ◽

Sram Cell ◽

Nanoscale Range

The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

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Reliability-Aware Design of Spike-Event Neuromorphic Circuits

10.36227/techrxiv.15141537 ◽

2021 ◽

Author(s):

Jani Babu Shaik ◽

Siona Menezes Picardo ◽

Sonal Singhal ◽

Nilesh Goel

Keyword(s):

Large Scale ◽

Vlsi Circuits ◽

Performance Parameters ◽

Carrier Injection ◽

Neuromorphic Circuits ◽

Integrate And Fire ◽

Bias Temperature Instability ◽

Large Scale Integration ◽

Silicon Neurons ◽

Scale Integration

Very Large Scale Integration (VLSI) based neuromorphic circuits also known as Silicon Neurons (SiNs) emulate the electrophysiological behavior of biological neurons. With the advancement in technology, neuromorphic systems also lead to various reliability issues and hence making their study important. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are the two major reliability issues present in VLSI circuits. In this work, we have investigated the combined effect of BTI and HCI on the two types of integrate-and-fire based SiNs namely (a) Axon-Hillock and (b) Simplified Leaky integrate-and-fire circuits using their key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. Proposed reliability-aware designs show negligible deviation in performance parameters after aging. The time-zero process variability analysis is also carried out for proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared.<br>

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High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.713-715.1042 ◽

2015 ◽

Vol 713-715 ◽

pp. 1042-1047

Author(s):

Xiao Ying Deng ◽

Yan Yan Mo ◽

Jian Hui Ning

Keyword(s):

Power Dissipation ◽

High Speed ◽

Large Scale ◽

Supply Voltage ◽

Operating Conditions ◽

Cmos Process ◽

Flip Flop ◽

Sense Amplifier ◽

Operation Speed ◽

Circuits Vlsi

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

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NBTI and Leakage Reduction Using an Integer Linear Programming Approach

Journal of Circuits System and Computers ◽

10.1142/s0218126617501778 ◽

2017 ◽

Vol 26 (11) ◽

pp. 1750177

Author(s):

Zhiming Yang ◽

Yang Yu ◽

Yue Guan ◽

Chengcheng Zhang ◽

Xiyuan Peng

Keyword(s):

Linear Programming ◽

Integer Linear Programming ◽

Supply Voltage ◽

Leakage Power ◽

Vlsi Circuits ◽

Input Vector ◽

Programming Approach ◽

Leakage Reduction ◽

Bias Temperature Instability ◽

Scale Down

As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for VLSI circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for CMOS devices. Because both the NBTI and leakage are dependent on input vector of the circuit, we present an input vector control (IVC) method based on an integer linear programming (ILP) approach. A novel NBTI and leakage reduction criterion function as well as an ILP formulation are presented to simultaneously minimize the delay degradation and leakage power. Our proposed ILP formulation can be generated adaptively for different circuits that can help the designers find the optimal input vector conveniently. In addition, the proposed method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed method.

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Reliability-Aware Design of Spike-Event Neuromorphic Circuits

10.36227/techrxiv.15141537.v1 ◽

2021 ◽

Author(s):

Jani Babu Shaik ◽

Siona Menezes Picardo ◽

Sonal Singhal ◽

Nilesh Goel

Keyword(s):

Large Scale ◽

Vlsi Circuits ◽

Performance Parameters ◽

Carrier Injection ◽

Neuromorphic Circuits ◽

Integrate And Fire ◽

Bias Temperature Instability ◽

Large Scale Integration ◽

Silicon Neurons ◽

Scale Integration

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Identifying Critical Components in Large Scale Cyber Physical Systems

Proceedings of the IEEE/ACM 42nd International Conference on Software Engineering Workshops ◽

10.1145/3387940.3391473 ◽

2020 ◽

Cited By ~ 1

Author(s):

Aida Akbarzadeh ◽

Sokratis Katsikas

Keyword(s):

Large Scale ◽

Cyber Physical Systems ◽

Physical Systems ◽

Critical Components

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COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

Journal of Circuits System and Computers ◽

10.1142/s0218126614501084 ◽

2014 ◽

Vol 23 (08) ◽

pp. 1450108 ◽

Cited By ~ 8

Author(s):

VANDANA NIRANJAN ◽

ASHWANI KUMAR ◽

SHAIL BALA JAIN

Keyword(s):

Low Power ◽

Large Scale ◽

Low Voltage ◽

Supply Voltage ◽

High Gain ◽

Signal Frequency ◽

Output Impedance ◽

Self Cascode ◽

Intrinsic Gain ◽

Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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