scholarly journals A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 253
Author(s):  
Dong Wang ◽  
Jian Luan ◽  
Xuan Guo ◽  
Lei Zhou ◽  
Danyu Wu ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Open Loop ◽  
Total Power ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Self Calibration ◽  
Differential Nonlinearity ◽  
Bicmos Technology ◽  
Sige Bicmos

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

scholarly journals A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 421
Author(s):  
Min-Jae Seo
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Open Loop ◽  
Sar Adc ◽  
Total Power ◽  
Control Logic ◽  
Analog To Digital ◽  
The One ◽  
And Control

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

scholarly journals A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1733
Author(s):  
Hanbo Jia ◽  
Xuan Guo ◽  
Xuqiang Zheng ◽  
Xiaodi Xu ◽  
Danyu Wu ◽  
...  
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nyquist Frequency ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Differential Nonlinearity

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

scholarly journals 10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 563
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Communication Systems ◽  
Power Efficiency ◽  
High Speed ◽  
Closed Loop ◽  
Dynamic Range ◽  
Data Converters ◽  
Fully Differential ◽  
Biquad Filter ◽  
Bicmos Technology ◽  
Sige Bicmos

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

scholarly journals A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 507 ◽  
Author(s):  
Junjie Wu ◽  
Jianhui Wu
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Total Power ◽  
Measurement Results ◽  
Spurious Free Dynamic Range ◽  
Back Ground ◽  
Static Power ◽  
Asynchronous Sar ◽  
Analogue To Digital ◽  
Ground Calibration

A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions.

scholarly journals A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 375
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Successive Approximation ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Adaptive Power

A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

scholarly journals ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

2019 ◽  
Vol 8 (3) ◽  
Author(s):  
Arash Rezapour ◽  
Mohammad Bagher Tavakoli ◽  
Farbod Setoudeh
Keyword(s):  
Power Supply ◽  
Data Transfer ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Analysis And Design ◽  
Second Stage ◽  
Total Power Consumption

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

scholarly journals Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Rongzong Kang ◽  
Pengwu Tian ◽  
Hongyi Yu
Keyword(s):  
Compressed Sensing ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Digital Converter ◽  
Analog To Digital ◽  
Sensing System ◽  
Spurious Free Dynamic Range ◽  
Simulation Results ◽  
The Impact ◽  
Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

scholarly journals Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1058
Author(s):  
Samuel B.S. Lee ◽  
Hang Liu ◽  
Kiat Seng Yeo ◽  
Jer-Ming Chen ◽  
Xiaopeng Yu
Keyword(s):  
Dynamic Range ◽  
Third Order ◽  
Transimpedance Amplifiers ◽  
Variable Gain ◽  
Gain Variation ◽  
Bicmos Technology ◽  
Capacitive Load ◽  
Sige Bicmos ◽  
Amplifier Stage ◽  
On Chip

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

An E-band Variable Gain Amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Dynamic Range ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Control Range ◽  
Variable Gain ◽  
Bicmos Technology ◽  
Commercial Technology ◽  
Sige Bicmos ◽  
Analysis Design

Abstract Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a −11.5 dBm input 1 dB compression point have been measured.

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