scholarly journals Low-Noise Programmable Voltage Source

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1245
Author(s):  
Krzysztof Achtenberg ◽  
Janusz Mikołajczyk ◽  
Carmine Ciofi ◽  
Graziella Scandurra ◽  
Zbigniew Bielecki

This paper presents the design and testing of a low-noise programmable voltage source. Such a piece of instrumentation is often required as part of the measurement setup needed to test electronic devices without introducing noise from the power supply (such as photodetectors, resistors or transistors). Although its construction is based on known configurations, here the discussion is focused on the characterization and the minimization of the output noise, especially at very low frequencies. The design relies on a digital-to-analog converter, proper lowpass filters, and a low-noise Junction Field-Effect Transistors (JFET) based voltage follower. Because of the very low level of output noise, in some cases we had to resort to cross-correlation in order to reduce the background noise of the amplifiers used for the characterization of the programmable source. Indeed, when two paralleled IF9030 JFETs are used in the voltage follower, the output noise can be as low as 3 nV/√Hz, 0.6 nV/√Hz and 0.4 nV/√Hz at 1 Hz, 10 Hz and 100 Hz, respectively. The output voltage drift was also characterized and a stability of ±25 µV over 3 h was obtained. In order to better appreciate the performance of the low-noise voltage source that we have designed, its noise performances were compared with those of a set-up based on one of the best low-noise solid-state voltage regulators available on the market. Actual measurements of the current noise in a type-II superlattice photodetector are reported in which the programmable source was used to provide the voltage bias to the device.

Author(s):  
Sigit Yuwono ◽  
Arie Van Staveren

The design of a low-noise and low-power second-order bandgap reference voltage source using a linear combination of two base-emitter voltages with only one scaling factor is treated. The design takes into account the temperature dependency of the resistors and the finite current gain of BJT�s. The circuit is integrated in a CMOS process. The output voltage is approximately 140 mV with an average temperature dependency of 22.5 ppm/K in the range of 0�C to 120�C. Its equivalent output noise voltage is 57.6nV/vHz. The total current consumption is about 115 �A from a 2V voltage-supply.Keywords: bandgap reference, negative feedback, systematic design.


2006 ◽  
Vol 3 (1) ◽  
pp. 27
Author(s):  
Mustaffa Samad

The Internet has been an integral part of the Information and Communication Technology (ICT) community in recent years. New internet users have been growing steadily over the years. This has lead to the depletion of new Internet Protocol (IP) addresses worldwide. To overcome this predicament, the new Internet Protocol version 6 (IPv6) had been introduced. The existing Internet Protocol version 4 (IPv4) is expected to be eventually replaced by this IPv6. The changeover from IPv4 to IPv6 is expected to be implemented progressively. During this transition period, these two protocols are expected to coexist for a number of years. IPv4-to-IPv6 transition tools have been designed to facilitate a smooth transition from IPv4 to IPv6. The two most basic IPv4-to-IPv6 transition tools available are the hybrid stack mechanism and tunneling. Tunneling is the encapsulation of IPv6 traffic within IPv4 packets so they can be sent over an IPv4 infrastructure. This project was initiated to set up an experimental IPv6 testbed, in order to study the performance as well as transition and migration issues of IPv6 networks under controlled conditions. This paper looks at how tunneling can be performed over existing internetwork infrastructure at Fakulti Kejuruteraan Elektrik (FKE), UiTM.


2006 ◽  
Vol 53 (5) ◽  
pp. 3004-3012 ◽  
Author(s):  
G.-F. Dalla Betta ◽  
M. Boscardin ◽  
F. Fenotti ◽  
L. Pancheri ◽  
C. Piemonte ◽  
...  

2021 ◽  
Author(s):  
Darshil Patel

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.


2021 ◽  
Vol 18 (3) ◽  
pp. 271-289
Author(s):  
Evgeniia Bulycheva ◽  
Sergey Yanchenko

Harmonic contributions of utility and customer may feature significant variations due to network switchings and changing operational modes. In order to correctly define the impacts on the grid voltage distortion the frequency dependent impedance characteristic of the studied network should be accurately measured in the real-time mode. This condition can be fulfilled by designing a stimuli generator measuring the grid impedance as a response to injected interference and producing time-frequency plots of harmonic contributions during considered time interval. In this paper a prototype of a stimuli generator based on programmable voltage source inverter is developed and tested. The use of ternary pulse sequence allows fast wide-band impedance measurements that meet the requirements of real-time assessment of harmonic contributions. The accuracy of respective analysis involving impedance determination and calculation of harmonic contributions is validated experimentally using reference characteristics of laboratory test set-up with varying grid impedance.


2021 ◽  
Author(s):  
Kenji Ohmori ◽  
Shuhei Amakawa

Characterization of broadband noise of MOSFETs from room temperature down to 120 K in fine temperature steps is presented. A MOSFET is mounted on a reusable printed circuit board vehicle with a built-in low-noise amplifier, and the vehicle is loaded into a cryogenic chamber. The vehicle allows noise measurement in the frequency range from 50 kHz to 100 MHz. At low frequencies, it enables extraction of activation energies associated with electron trapping sites. At high frequencies, as has been suggested by noise figure measurements, the white noise of MOSFETs is shown to be dominated by the shot noise, which has much weaker temperature dependence than the thermal noise. The shot noise will be a problematic noise source in broadband RF CMOS circuits operating at cryogenic temperatures.<div><br></div>


2001 ◽  
Vol 665 ◽  
Author(s):  
A. Ullmann ◽  
J. Ficker ◽  
W. Fix ◽  
H. Rost ◽  
W. Clemens ◽  
...  

ABSTRACTIntegrated plastic circuits (IPCs) will become an integral component of future low cost electronics. For low cost processes IPCs have to be made of all-polymer Transistors. We present our recent results on fabrication of Organic Field-Effect Transistors (OFETs) and integrated inverters. Top-gate transistors were fabricated using polymer semiconductors and insulators. The source-drain structures were defined by standard lithography of Au on a flexible plastic film, and on top of these electrodes, poly(3-alkylthiophene) (P3AT) as semiconductor, and poly(4-hydroxystyrene) (PHS) as insulator were homogeneously deposited by spin-coating. The gate electrodes consist of metal contacts. With this simple set-up, the transistors exhibit excellent electric performance with a high source-drain current at source - drain and gate voltages below 30V. The characteristics show very good saturation behaviour for low biases and are comparable to results published for precursor pentacene. With this setup we obtain a mobility of 0.2cm2/Vs for P3AT. Furthermore, we discuss organic integrated inverters exhibiting logic capability. All devices show shelf-lives of several months without encapsulation.


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