scholarly journals A Nano-Power 0.5 V Event-Driven Digital-LDO with Fast Start-Up Burst Oscillator for SoC-IoT

2020 ◽  
Vol 10 (4) ◽  
pp. 41
Author(s):  
Christos Konstantopoulos ◽  
Thomas Ussmueller
Keyword(s):  
Power Efficiency ◽  
High Gain ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Clock Generation ◽  
Start Up ◽  
Fast Start ◽  
Main Regulator ◽  
Gain Stage

Towards the integration of Digital-LDO regulators in the ultra-low-power System-On-Chip Internet-of-Things architecture, the D-LDO architecture should constitute the main regulator for powering digital and mixed-signal loads including the SoC system clock. Such an implementation requires an in-regulator clock generation unit that provides an autonomous D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the oscillating frequency, this work presents a design with nano-power consumption, fabricated with an active area of 0.035 mm2 at a 55-nm Global Foundries CMOS process that introduces a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of D-LDO frequency. In combination with linear search coarse regulation and asynchronous fine regulation, it succeeds 558 nA minimum quiescent current with CL 75 pF, maximum current efficiency of 99.2% and 1.16x power efficiency improvement compared to analog counterpart oriented to SoC-IoT loads.

Energy-Efficient Gain Cell and Its Applications in the Limiting Amplifier and Ring Oscillator for Gbps Communications

2017 ◽  
Vol 27 (01) ◽  
pp. 1850007 ◽  
Author(s):  
Yutong Ying ◽  
Xuefei Bai ◽  
Fujiang Lin
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Oscillation Frequency ◽  
High Gain ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Gain Bandwidth ◽  
Limiting Amplifier ◽  
High Oscillation Frequency ◽  
Good Energy

This paper presents a low-power, high gain-bandwidth product (GBW) gain cell for gigabits-per-second communications. Based on this gain cell, a large GBW limiting amplifier (LA) and two types of high oscillation-frequency ring oscillators (ROs) are implemented with good energy efficiencies. Fabricated in the 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed LA can support 1.25[Formula: see text]Gbps data-rate with a measured GBW of 338[Formula: see text]GHz under 5[Formula: see text]mW. The proposed single- and multi-loop ROs obtain a simulated typical oscillation frequency of 5.26[Formula: see text]GHz and 6.96[Formula: see text]GHz, respectively, under 6.2 mW, which is less than one-eighth the power consumption of published ROs at similar frequencies in the same process.

scholarly journals Ultra-low Power Integrated Analog Front-End for ISFET-based Sensors

2018 ◽  
Vol 13 (3) ◽  
pp. 1-11
Author(s):  
Ronaldo Martins Da Ponte ◽  
Angélica Denardi De Barros ◽  
José Alexandre Diniz ◽  
Fernando Rangel De Sousa
Keyword(s):  
Pulse Frequency ◽  
The Body ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Case Scenario ◽  
Worst Case ◽  
Ultra Low Power ◽  
Front End ◽  
Analog Front End ◽  
Testing Solution

In this paper, an integrated analog front-end (AFE) to condition ISFET-based sensors is presented. This is accomplished by a pH-controlled ring oscillator (pHCO) that produces a pulse frequency-modulated signal proportional to pH of a testing solution. The AFE was designed in a 180-nm standard CMOS process and a Verilog-based model was used to aid electrochemical simulations. Sensorless measurements of the chip were carried out on the oscilloscope and results revealed a digitally-represented signal with 70 MHz/V of responsivity, under a sweeping voltage from 1.0 V to 1.2 V, and a worst-case scenario of 69.4 µW for the overall power consumption. Moreover, the circuit topology circumvents the body effect problems, suppress the use of OP-AMPs or ADCs, and allows monolithic integration.

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator

2017 ◽  
Vol 26 (12) ◽  
pp. 1750193 ◽  
Author(s):  
Xin Cheng ◽  
Hongyu Liang ◽  
Longjie Du ◽  
Zhang Zhang ◽  
Maoxiang Yi ◽  
...  
Keyword(s):  
Transient Response ◽  
Cmos Process ◽  
Heavy Load ◽  
Ultra Low Power ◽  
Chip Area ◽  
Error Amplifier ◽  
Light Load ◽  
Gain Stage ◽  
Ldo Regulator ◽  
Overshoot And Undershoot

This paper proposes an output-capacitorless low-dropout (LDO) regulator with ultra-low quiescent power. It applies an adaptive error amplifier to improve the bandwidth and transient response during heavy load, and a second gain stage to improve the stability during light load. Furthermore, an overshoot and undershoot reduction circuit is used to shorten the settling time when output load is changed. The LDO is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process and occupies a chip area of 0.06[Formula: see text]mm2. The LDO is measured to output a stable voltage at 1.6[Formula: see text]V with a quiescent power of 1.8[Formula: see text][Formula: see text]W. The experimental results also show a good transient response.

ULTRA-LOW POWER BOOST CONVERTER WITH CONSTANT ON-TIME-BASED MPPT FOR ENERGY HARVESTING APPLICATIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450027 ◽  
Author(s):  
MINGYANG CHEN ◽  
MENGLIAN ZHAO ◽  
QING LIU ◽  
LU WANG ◽  
XIAOBO WU
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Efficiency ◽  
Input Voltage ◽  
Boost Converter ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Voltage Range ◽  
Point Tracking ◽  
Power Point

An ultra-low power boost converter for energy harvesting applications is introduced in this brief. The idle power dissipation is reduced to 800 nW by using a novel output voltage detector (OVD) which is insensitive to temperature variation and process deviation. Furthermore, a constant on-time (COT)-based hysteretic burst mode controller with maximum power point tracking (MPPT) technique is developed to ensure high power efficiency for a wide input voltage range. After startup, the input voltage can be set as low as 30 mV. The whole system is designed and fabricated in SMIC 0.18 μm CMOS process, the end-to-end power efficiency of this converter can reach 49% at 350 mV input voltage and 65% at 750 mV input voltage.

scholarly journals Low Voltage Delay Element with Dynamic Biasing Technique for Fully Integrated Cold-Start in Battery-Assistance DC Energy Harvesting Systems

2020 ◽  
Vol 10 (19) ◽  
pp. 6993 ◽  
Author(s):  
Zushuai Xie ◽  
Zhiqiang Wu ◽  
Jianhui Wu
Keyword(s):  
Energy Harvesting ◽  
Low Voltage ◽  
Cold Start ◽  
The Body ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Delay Element ◽  
Fully Integrated ◽  
Start Up ◽  
Harvesting Systems

This paper proposes an ultra-low voltage delay element for battery-assistance DC energy harvesting systems. By inserting a low voltage level shifter (VLS), a wider voltage range is obtained to bias the body of the delay element. Thus, both the voltage transfer curve (VTC) and the DC gain of the delay element are enhanced. Due to the introduction of the VLS, the cold start-up ring oscillator constituted by the proposed delay element can achieve oscillation under an extremely low input voltage. The fully integrated cold start-up ring oscillator with 21 stages of the proposed element is implemented in a standard 180 nm complementary metal oxide semiconductor (CMOS) process. The post-layout experimental results indicate that the cold start-up ring oscillator can retain oscillation when the power supply voltage (VDD) is 24 mV under a typical corner at room temperature. The output voltage swing of the cold start-up ring oscillator based on the proposed delay element is improved by more than 55% under VDD = 40 mV compared with a stacked inverter-based cold start-up ring oscillator. Monte Carlo (MC) simulation from 100 samples shows the enhanced output swing with the proposed delay element under process variation.

scholarly journals A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2059
Author(s):  
Xuan Thanh Pham ◽  
Ngoc Tan Nguyen ◽  
Van Truong Nguyen ◽  
Jong-Wook Lee
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Noise ◽  
Efficiency Factor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Common Mode ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Servo Loop

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

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