scholarly journals Heterogeneous Wafer Bonding Technology and Thin-Film Transfer Technology-Enabling Platform for the Next Generation Applications beyond 5G

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 946
Author(s):  
Zhihao Ren ◽  
Jikai Xu ◽  
Xianhao Le ◽  
Chengkuo Lee
Keyword(s):  
Thin Film ◽  
Wafer Bonding ◽  
Composite Structures ◽  
High Speed ◽  
Silicon On Insulator ◽  
Wearable Electronics ◽  
Next Generation ◽  
Bonding Technology ◽  
Film Transfer ◽  
Bandgap Semiconductors

Wafer bonding technology is one of the most effective methods for high-quality thin-film transfer onto different substrates combined with ion implantation processes, laser irradiation, and the removal of the sacrificial layers. In this review, we systematically summarize and introduce applications of the thin films obtained by wafer bonding technology in the fields of electronics, optical devices, on-chip integrated mid-infrared sensors, and wearable sensors. The fabrication of silicon-on-insulator (SOI) wafers based on the Smart CutTM process, heterogeneous integrations of wide-bandgap semiconductors, infrared materials, and electro-optical crystals via wafer bonding technology for thin-film transfer are orderly presented. Furthermore, device design and fabrication progress based on the platforms mentioned above is highlighted in this work. They demonstrate that the transferred films can satisfy high-performance power electronics, molecular sensors, and high-speed modulators for the next generation applications beyond 5G. Moreover, flexible composite structures prepared by the wafer bonding and de-bonding methods towards wearable electronics are reported. Finally, the outlooks and conclusions about the further development of heterogeneous structures that need to be achieved by the wafer bonding technology are discussed.

Nondestructive Thin Film Defect Analysis of Silicon‐on‐Insulator Layers Made by Zone‐Melt Recrystallization and Wafer Bonding

1990 ◽  
Vol 137 (12) ◽  
pp. 3975-3977
Author(s):  
M. J. J. Theunissen ◽  
A. H. Goemans ◽  
A. J. R. de Kock ◽  
J. Haisma ◽  
C. W. T. Bulle‐Lieuwma ◽  
...  
Keyword(s):  
Thin Film ◽  
Wafer Bonding ◽  
Silicon On Insulator ◽  
Defect Analysis ◽  
Insulator Layers ◽  
Film Defect ◽  
Zone Melt

scholarly journals Optimization of the Ion-Cut Process in Si and SiC

2000 ◽  
Vol 647 ◽  
Author(s):  
O. W. Holland ◽  
D. K. Thomas ◽  
R. B. Gregory
Keyword(s):  
Thin Film ◽  
Elevated Temperature ◽  
Ion Implantation ◽  
Wafer Bonding ◽  
Silicon On Insulator ◽  
Critical Dose ◽  
Wide Range ◽  
Temperature Irradiation ◽  
Film Separation

AbstractH+-implantation is the basis for an ion-cut process, which combines hydrophilic wafer bonding, to produce heterostructures over a wide range of materials. This process has been successfully applied in Si to produce a commercial silicon-on-insulator material. The efficacy of implantation to produce thin-film separation was studied by investigation of H+-induced exfoliation in Si and SiC. Experiments were done to isolate the effects of the hydrogen chemistry from that of implant damage. Damage is manipulated independently of H+ dosage by a variety of techniques ranging from elevated temperature irradiation to a two-step implantation scheme in Si, and the use of channeled-ion implantation in SiC. The results will demonstrate that such schemes can significantly reduce the critical dose for exfoliation.

Improving High-Speed Nanomaterials Printing With Sub-Process-Decoupled Gravure Printer Design

2017 ◽  
Author(s):  
William Scheideler ◽  
Vivek Subramanian
Keyword(s):  
Thin Film ◽  
Contact Mechanics ◽  
Smart Materials ◽  
High Speed ◽  
Large Scale ◽  
Squeezing Flow ◽  
Print Quality ◽  
Wearable Electronics ◽  
Gravure Printing ◽  
Artifact Formation

Printing technologies are attractive methods for high-throughput additive manufacturing of nanomaterials-based thin film electronics. Roll-to-roll (R2R) compatible techniques such as gravure printing can operate at high-speed (1–10 m/s) and high-resolution (< 10 μm) to drive down manufacturing costs and produce higher quality flexible electronic devices. However, large-scale deployment of printed wireless sensors, flexible displays, and wearable electronics, will require greater understanding of the printing physics of nanomaterial-based inks in order to improve the resolution, reliability, and uniformity of printed systems. In this study, we designed and constructed a custom sheet-fed gravure printer which features registered multilayer printing for nanomaterial exploration and thin film device development. The design allows precise, independent control of the speeds and forces of each of the subprocesses of gravure (ink filling, wiping, and transfer), enabling novel experimental controls for dissecting the printing process fluid mechanics. We use these new capabilities to investigate the primary artifacts which distort printed nanomaterial patterns, such as dragout tails, edge roughness, and pinholes. These artifacts are studied as a function of print parameters such as contact pressure, wiping speed, and transfer speed, by printing silver nanoparticle ink to form continuous features with dimensions in the range of 100 μm to 10 mm. We found that the contact mechanics of the ink transfer process have a strong influence on the formation of dragout artifacts, indicating the presence of a transfer-driven squeezing flow which distorts the trailing edges of features. By engineering the transfer contact mechanics with varying rubber substrate backing stiffness, we found it is also possible to suppress this artifact formation for a particular nanomaterial ink. The improved areal uniformity and print quality achieved using these methods highlight the potential for gravure printing to be a versatile nano-manufacturing tool for patterning a variety of thin film smart materials. We also hope that the open-source printer designs presented here can serve to accelerate the development of high-speed nanomaterial printing.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

In Situ microscopy of the anodic etching of silicon

1995 ◽  
Vol 53 ◽  
pp. 232-233
Author(s):  
Frances M. Ross ◽  
Peter C. Searson
Keyword(s):  
Composite Structures ◽  
High Surface ◽  
High Surface Area ◽  
Chemical Properties ◽  
Selective Etching ◽  
Silicon On Insulator ◽  
Second Phase ◽  
Porous Layers ◽  
New Class ◽  
Porous Semiconductors

Porous semiconductors represent a relatively new class of materials formed by the selective etching of a single or polycrystalline substrate. Although porous silicon has received considerable attention due to its novel optical properties1, porous layers can be formed in other semiconductors such as GaAs and GaP. These materials are characterised by very high surface area and by electrical, optical and chemical properties that may differ considerably from bulk. The properties depend on the pore morphology, which can be controlled by adjusting the processing conditions and the dopant concentration. A number of novel structures can be fabricated using selective etching. For example, self-supporting membranes can be made by growing pores through a wafer, films with modulated pore structure can be fabricated by varying the applied potential during growth, composite structures can be prepared by depositing a second phase into the pores and silicon-on-insulator structures can be formed by oxidising a buried porous layer. In all these applications the ability to grow nanostructures controllably is critical.

Leakage current models of thin film silicon-on-insulator devices

1998 ◽  
Vol 72 (10) ◽  
pp. 1199-1201 ◽  
Author(s):  
Hank Shin ◽  
Stella Hong ◽  
Tom Wetteroth ◽  
Syd R. Wilson ◽  
Dieter K. Schroder
Keyword(s):  
Thin Film ◽  
Leakage Current ◽  
Silicon On Insulator ◽  
Thin Film Silicon

Top-down Fabricated Gold Nanostrip on Silicon-on-insulator Wafer: A Promising Building Block towards Ultra-compact Optical Device

Nanoscale ◽  
2020 ◽  
Author(s):  
Fuping Zhang ◽  
Weikang Liu ◽  
Li Chen ◽  
Zhiqiang Guan ◽  
Hongxing Xu
Keyword(s):  
Optical Communication ◽  
Data Transmission ◽  
Building Block ◽  
High Speed ◽  
Large Data ◽  
Low Energy ◽  
Silicon On Insulator ◽  
Fundamental Building Block ◽  
Low Energy Consumption ◽  
Controllable Fabrication

he plasmonic waveguide is the fundamental building block for high speed, large data transmission capacity, low energy consumption optical communication and sensing. Controllable fabrication and simultaneously optimization of the propagation...

Sign in / Sign up

Export Citation Format

Share Document