scholarly journals A Review of Sharp-Switching Band-Modulation Devices

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1540
Author(s):  
Sorin Cristoloveanu ◽  
Joris Lacord ◽  
Sébastien Martinie ◽  
Carlos Navarro ◽  
Francisco Gamiz ◽  
...  
Keyword(s):  
Room Temperature ◽  
Recent Progress ◽  
Low Voltage ◽  
Electrostatic Discharge ◽  
Silicon On Insulator ◽  
Pin Diode ◽  
Fully Depleted ◽  
Reconfigurable Circuits ◽  
Low Voltage Operation ◽  
Electrostatic Doping

This paper reviews the recently-developed class of band-modulation devices, born from the recent progress in fully-depleted silicon-on-insulator (FD-SOI) and other ultrathin-body technologies, which have enabled the concept of gate-controlled electrostatic doping. In a lateral PIN diode, two additional gates can construct a reconfigurable PNPN structure with unrivalled sharp-switching capability. We describe the implementation, operation, and various applications of these band-modulation devices. Physical and compact models are presented to explain the output and transfer characteristics in both steady-state and transient modes. Not only can band-modulation devices be used for quasi-vertical current switching, but they also show promise for compact capacitorless memories, electrostatic discharge (ESD) protection, sensing, and reconfigurable circuits, while retaining full compatibility with modern silicon processing and standard room-temperature low-voltage operation.

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

2014 ◽  
Vol 778-780 ◽  
pp. 841-844 ◽  
Author(s):  
Koji Nakayama ◽  
Shuji Ogata ◽  
Toshihiko Hayashi ◽  
Tetsuro Hemmi ◽  
Atsushi Tanaka ◽  
...  
Keyword(s):  
High Voltage ◽  
Recovery Time ◽  
Carrier Lifetime ◽  
Low Voltage ◽  
Reduction Rate ◽  
Drift Region ◽  
Pin Diode ◽  
Fully Depleted ◽  
Fast Switching ◽  
Reverse Recovery Time

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.

Recent Progress in SOI Materials and Devices for VLSI Applications

1993 ◽  
Vol 316 ◽  
Author(s):  
H. H. Hosack
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Recent Progress ◽  
Low Voltage ◽  
Silicon On Insulator ◽  
Significant Interest ◽  
Significant Performance ◽  
Cmos Ic ◽  
Bulk Processing ◽  
Soi Technology

Silicon-On-Insulator (SOI) technology [1-4] has been shown to have significant performance and fabrication advantages over conventional bulk processing for a wide variety of large scale CMOS IC applications. Advantages in radiation environments has generated significant interest in this technology from military and space science communities [5,6]. Possible advantages of SOI technology for low power, low voltage and high performance circuit applications is under serious consideration by several commercial IC manufacturers [7,8].

RECENT PROGRESS OF FERROELECTRIC MEMORIES

2002 ◽  
Vol 12 (02) ◽  
pp. 315-323 ◽  
Author(s):  
HIROSHI ISHIWARA
Keyword(s):  
Recent Progress ◽  
Low Voltage ◽  
Random Access ◽  
Ferroelectric Materials ◽  
Basic Operation ◽  
Retention Characteristic ◽  
Low Voltage Operation ◽  
Cell Structures ◽  
Ferroelectric Memories ◽  
Non Destructive

Recent progress of ferroelectric random access memories (FeRAMs) is reviewed. First, novel ferroelectric materials, which are suitable for both low temperature crystallization and low voltage operation are introduced. Then, various cell structures in FeRAMs are discussed, in which particular attention is paid to non-destructive-readout-type cells such as a 1T-type cell composed of a single ferroelectric-gate field effect transistor. Finally, a novel 1T2C-type non-destructive-readout cell with good data retention characteristic is introduced and its basic operation is presented.

A silicon x- and gamma-ray detector for room temperature and low voltage operation

1982 ◽  
Vol 193 (1-2) ◽  
pp. 63-67 ◽  
Author(s):  
Massaya Yabe ◽  
Noritada Sato ◽  
Hiroshi Kamijo ◽  
Toshiaki Takechi ◽  
Fumio Shiraishi
Keyword(s):  
Room Temperature ◽  
Gamma Ray ◽  
Low Voltage ◽  
Low Voltage Operation ◽  
Gamma Ray Detector

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

Temporal color mixing and dynamic beam shaping with silicon metasurfaces

Science ◽  
2019 ◽  
Vol 365 (6450) ◽  
pp. 257-260 ◽  
Author(s):  
Aaron L. Holsteen ◽  
Ahmet Fatih Cihan ◽  
Mark L. Brongersma
Keyword(s):  
Antenna Arrays ◽  
Low Voltage ◽  
Beam Steering ◽  
Silicon On Insulator ◽  
Optical Systems ◽  
Optical Functions ◽  
Low Voltage Operation ◽  
Planar Form ◽  
Color Mixing ◽  
Continuous Dynamic

Metasurfaces offer the possibility to shape optical wavefronts with an ultracompact, planar form factor. However, most metasurfaces are static, and their optical functions are fixed after the fabrication process. Many modern optical systems require dynamic manipulation of light, and this is now driving the development of electrically reconfigurable metasurfaces. We can realize metasurfaces with fast (>105 hertz), electrically tunable pixels that offer complete (0- to 2π) phase control and large amplitude modulation of scattered waves through the microelectromechanical movement of silicon antenna arrays created in standard silicon-on-insulator technology. Our approach can be used to realize a platform technology that enables low-voltage operation of pixels for temporal color mixing and continuous, dynamic beam steering and light focusing.

scholarly journals Evidence of Limitations of the Transconductance-to-Drain-Current Method (gm/Id) for Transistor Sizing in 28 nm UTBB FD-SOI Transistors

2020 ◽  
Vol 10 (2) ◽  
pp. 17
Author(s):  
Leonardo Barboni
Keyword(s):  
Low Voltage ◽  
Current Method ◽  
Drain Current ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Thin Body ◽  
Fully Depleted ◽  
Circuit Simulator ◽  
Transistor Sizing ◽  
28 Nm

The transconductance-to-drain-current method is a transistor sizing methodology that is commonly used in CMOS technology. In this study, we explored by means of simulations, a case of study and three figures of merit used for the method, and we conclude for the first time that the method should be reformulated. The study has been performed on Ultra-Thin Body and Buried Fully Depleted Silicon-On-Insulator 28 nm low-voltage-threshold NFET commercial technology (UTBB FD-SOI), and the simulations were performed via Spectre Circuit Simulator, by using the device model-card. To our knowledge, no previous attempts have been made to assess the method capability, and we collected very important results that infer that the method should be reformulated or considered incomplete for use with this technology, which has an impact and ramifications on the field of process modeling, simulation and circuit design.

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