scholarly journals Use of High-Field Electron Injection into Dielectrics to Enhance Functional Capabilities of Radiation MOS Sensors

Sensors ◽  
2020 ◽  
Vol 20 (8) ◽  
pp. 2382
Author(s):  
Dmitrii V. Andreev ◽  
Gennady G. Bondarenko ◽  
Vladimir V. Andreev ◽  
Alexander A. Stolyarov
Keyword(s):  
High Field ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Particle Radiation ◽  
Charge Effects ◽  
Functional Capabilities ◽  
Ionization Radiation ◽  
Γ Rays ◽  
Radiation Sensors ◽  
Tunnel Injection

The paper suggests a design of radiation sensors based on metal-oxide-semiconductor (MOS) structures and p-channel radiation sensitive field effect transistors (RADFET) which are capable to function under conditions of high-field tunnel injection of electrons into the dielectric. We demonstrate that under these conditions, the dose sensitivity of the sensor can be significantly raised, and, besides, the intensity of radiation can be monitored in situ on the basis of determining the ionization current arising in the dielectric film. The paper proposes the model allowing to make a quantitative analysis of charge effects taking place in the radiation MOS sensors under concurrent influence of ionization radiation and high-field tunnel injection of electrons. Use of the model allows to properly interpret results of the radiation control. In order to test the designed sensors experimentally, we have utilized γ-rays, α-particle radiation, and proton beams. We have acquired experimental results verifying the enhancement of function capabilities of the radiation MOS sensors when these have been under high-field injection of electrons into the dielectric.

scholarly journals A Review of Semiconductor Based Ionising Radiation Sensors Used in Harsh Radiation Environments and Their Applications

Radiation ◽  
2021 ◽  
Vol 1 (3) ◽  
pp. 194-217
Author(s):  
Arijit Karmakar ◽  
Jialei Wang ◽  
Jeffrey Prinzie ◽  
Valentijn De Smedt ◽  
Paul Leroux
Keyword(s):  
Integrated Circuits ◽  
High Energy Physics ◽  
Field Effect Transistors ◽  
Random Access ◽  
Absorbed Dose ◽  
High Energy ◽  
Ionising Radiation ◽  
Oxide Semiconductor ◽  
Nand Flash ◽  
Radiation Sensors

This article provides a review of semiconductor based ionising radiation sensors to measure accumulated dose and detect individual strikes of ionising particles. The measurement of ionising radiation (γ-ray, X-ray, high energy UV-ray and heavy ions, etc.) is essential in several critical reliability applications such as medical, aviation, space missions and high energy physics experiments considering safety and quality assurance. In the last few decades, numerous techniques based on semiconductor devices such as diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs) and solid-state photomultipliers (SSPMs), etc., have been reported to estimate the absorbed dose of radiation with sensitivity varying by several orders of magnitude from μGy to MGy. In addition, the mitigation of soft errors in integrated circuits essentially requires detection of charged particle induced transients and digital bit-flips in storage elements. Depending on the particle energies, flux and the application requirements, several sensing solutions such as diodes, static random access memory (SRAM) and NAND flash, etc., are reported in the literature. This article goes through the evolution of radiation dosimeters and particle detectors implemented using semiconductor technologies and summarises the features with emphasis on their underlying principles and applications. In addition, this article performs a comparison of the different methodologies while mentioning their advantages and limitations.

Accelerated Testing of SiC Power Devices under High-Field Operating Conditions

2020 ◽  
Vol 1004 ◽  
pp. 992-997
Author(s):  
Daniel J. Lichtenwalner ◽  
Shadi Sabri ◽  
Edward Van Brunt ◽  
Brett Hull ◽  
Sei Hyung Ryu ◽  
...  
Keyword(s):  
High Field ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Short Circuit ◽  
Gate Oxide ◽  
Operating Conditions ◽  
Oxide Semiconductor ◽  
Normal Operation ◽  
Time Dependent Dielectric Breakdown ◽  
Stability Time

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

TEM study of Cosi2 formation via annealing of Co-Ti bilayers on Si

1995 ◽  
Vol 53 ◽  
pp. 464-465
Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier
Keyword(s):  
Thermal Instability ◽  
Lattice Mismatch ◽  
Field Effect Transistors ◽  
Contact Layer ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Surface Layers ◽  
Silicide Layer ◽  
Small Lattice ◽  
Buried Layers

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Sign in / Sign up

Export Citation Format

Share Document