scholarly journals Design of an Ultrasound Transceiver ASIC with a Switching-Artifact Reduction Technique for 3D Carotid Artery Imaging

Sensors ◽  
2020 ◽  
Vol 21 (1) ◽  
pp. 150
Author(s):  
Taehoon Kim ◽  
Fabian Fool ◽  
Djalma Simoes dos Santos ◽  
Zu-Yao Chang ◽  
Emile Noothout ◽  
...  
Keyword(s):  
Carotid Artery ◽  
High Voltage ◽  
Integrated Circuit ◽  
Imaging System ◽  
Field Effect Transistors ◽  
Acoustic Pulse ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Clock Feedthrough ◽  
Imaging Artifacts

This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.

Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Logic Synthesis ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Timing Models ◽  
High Temperature Operation

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

A Non-Destructive and Effective Metrology to Automatically Monitor Kink Effect of MOSFETs

2011 ◽  
Vol 291-294 ◽  
pp. 2910-2913
Author(s):  
Mu Chun Wang ◽  
Hsin Chia Yang
Keyword(s):  
Integrated Circuit ◽  
Analog Circuit ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Shallow Trench Isolation ◽  
Kink Effect ◽  
Local Oxidation ◽  
Trench Isolation ◽  
Second Derivative Method ◽  
Non Destructive

The kink effect is a harassed issue existing in metal-oxide-semiconductor field-effect transistors (MOSFETs) and usually degrades the whole chip performance, especially in analog circuit operation. No matter what the device isolation is with local oxidation of silicon (LOCOS) process or shallow trench isolation (STI) process, this effect more or less depicts. How to sense this effect in integrated-circuit (IC) mass-production is a crucial event. Through a second derivative method on Ids versus Vgs curves in MOSFET device, the unhealthy devices can be effectively screened out with the application of programmable auto testers. Using this derivative metrology implemented into the measurement testers, the distribution of kink devices on wafer is easily plotted. This information is very precious to the semiconductor process engineers in process improvement, too.

Complementary metal oxide semiconductor compatible high-voltage transistors

1987 ◽  
Vol 65 (8) ◽  
pp. 1003-1008
Author(s):  
P. Kempf ◽  
R. Hadaway ◽  
J. Kolk
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Process Model ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Measurements ◽  
Cmos Transistors

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

A SUBTHRESHOLD ANALOG MOS CIRCUIT FOR LOTKA–VOLTERRA CHAOTIC OSCILLATOR

2006 ◽  
Vol 16 (01) ◽  
pp. 207-212 ◽  
Author(s):  
TETSUYA ASAI ◽  
TAISHI KAMIYA ◽  
TETSUYA HIROSE ◽  
YOSHIHITO AMEMIYA
Keyword(s):  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Chaotic Oscillator ◽  
Mathematical Form ◽  
Subthreshold Region ◽  
Analog Ic ◽  
Quantitative Studies ◽  
System Variables

We fabricated an analog integrated circuit (IC) that implements the Lotka–Volterra (LV) chaotic oscillator presented by Mimura and Kan-on [1986]. The LV system describes periodic or chaotic behaviors in prey–predator systems in simple mathematical form, and is suitable for analog IC implementation [Asai et al., 2003]. The proposed circuit consists of a small number of metal-oxide-semiconductor field-effect transistors (MOS FETs) operating in their subthreshold region. A new scaling factor of system variables, which was not discussed in [Asai et al., 2003], is also introduced for quantitative studies of designing practical hardware LV systems.

scholarly journals Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1205 ◽  
Author(s):  
Iván Zamora ◽  
Eyglis Ledesma ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
Integrated Circuit ◽  
Imaging System ◽  
Ultrasonic Transducer ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Axial Distance ◽  
Cmos Integrated Circuit ◽  
Front End ◽  
Analog Front End

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

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