Impact of gate electrode formation process on Al2O3/GaN interface properties and channel mobility

Author(s):  
Yuto Ando ◽  
Manato Deki ◽  
Hirotaka Watanabe ◽  
Noriyuki Taoka ◽  
Atsushi Tanaka ◽  
...  
2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.


ESSDERC ’89 ◽  
1989 ◽  
pp. 366-369 ◽  
Author(s):  
B. Piot ◽  
A. Straboni ◽  
B. Vuillermoz ◽  
K. Barla ◽  
M. Berenguer ◽  
...  

2002 ◽  
Vol 742 ◽  
Author(s):  
Hiroshi Yano ◽  
Taichi Hirao ◽  
Tsunenobu Kimoto ◽  
Hiroyuki Matsunami

ABSTRACTThe interface properties of MOS capacitors and MOSFETs were characterized using the (0001), (1120), and (0338) faces of 4H-SiC. (0001) and (1120) correspond to (111) and (110) in cubic structure. (0338) is semi-equivalent to (100). The interface states near the conduction band edge are discussed based on the capacitance and conductance measurements of n-type MOS capacitors at a low temperature and room temperature. The (0338) face indicated the smallest interface state density near the conduction band edge and highest channel mobility in n-channel MOSFETs among these faces.


2004 ◽  
Vol 815 ◽  
Author(s):  
T. Kimoto ◽  
Y. Kanzaki ◽  
M. Noborio ◽  
H. Kawano ◽  
H. Matsunami

Abstract4H-SiC(0001), (000-1), and (11-20) have been directly oxidized by N2O at 1300°C, and the MOS interfaces have been characterized. The interface state density has been significantly reduced by N2O oxidation on any face, compared to conventional wet O2 oxidation at 1150°C. Planar n-channel MOSFETs fabricated on lightly-doped 4H-SiC(0001), (000-1) and (11-20) faces have shown an effective channel mobility of 26, 43, and 78 cm2/Vs, respectively. The mobility decreased with increasing the doping concentration of p-body. SIMS analyses have revealed a clear pile-up of nitrogen atoms near the MOS interface. The thickness of interfacial SiCxOy layer can be decreased by utilizing N2O oxidation. The crystal face dependence of interface structure is discussed.


Author(s):  
Yue-Gie Liaw ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Chii-Wen Chen ◽  
Deshi Li ◽  
...  

The length of Source/Drain (S/D) extension (LSDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer LSDE pFinFET provides a larger series resistance and degrades the drive current (IDS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter LSDE plus the shorter channel length demonstrates a higher trans-conductance (Gm) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer LSDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current. DOI: 10.21883/FTP.2017.12.45190.8421


2013 ◽  
Vol 50 (4) ◽  
pp. 281-284
Author(s):  
K. Tuokedaerhan ◽  
R. Tan ◽  
K. Kakushima ◽  
P. Ahmet ◽  
Y. Kataoka ◽  
...  

2005 ◽  
Vol 483-485 ◽  
pp. 805-808
Author(s):  
Mitsuo Okamoto ◽  
Seiji Suzuki ◽  
Makoto Kato ◽  
Tsutomu Yatsuo ◽  
Kenji Fukuda

We have fabricated lateral RESURF MOSFETs on 4H-SiC(0001) Si-face and (000-1) C-face substrates, and compared those properties. The channel mobility of a lateral test MOSFET on a C-face was 41 cm2/Vs, which was much higher than 5 cm2/Vs for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was improved to 79 mΩcm2 as comparison with 2400 mΩcm2 for Si-face. The breakdown voltage was 490V for Si-face and 460V for C-face, which was 82% and 79% of the designed breakdown voltage of 600V, respectively. The device breakdown occurred destructively at the gate electrode edge.


Author(s):  
Masaru Itakura ◽  
Noriyuki Kuwano ◽  
Kensuke Oki

The low temperature phase of Pd5Ce (L-Pd5Ce) has a one-dimensional long period superstructure (1D-LPS) derived from Ll2. The periodic antiphase boundaries (APBs) are parallel to (110) planes and have a shift vector of 1/2[110]. Hereafter, the indices are referred to the basic lattices of Ll2 As insertion of the APB causes a change in composition, such an APB is called “non-conservative”. Then, a domain size M depends upon the Ce concentration in the alloy. It was found that M increases also with temperature. The temperature dependency of M is attributed to a change of the degree of order within the antiphase domains. In this work, morphology of the non-conservative APBs is observed to clarify the formation process of the 1D-LPS.The alloy of Pd-16.7 at%Ce was prepared by arc melting in argon atmosphere. Disc specimens made from the alloy ingot were first held at 985 K for 260 ks and quenched in iced water to obtain the state of M=∞ or Ll2, followed by annealing for various lengths of time. The annealing temperature was 873 K where the equilibrium value for M is about 3 in unit of (110) lattice spacing of Ll2. Observation was carried out using microscopes JEM-2000FX, JEM-4000EX (HVEM Lab., Kyushu Univ.) and JEM-2000EX (Dept. of Mater. Sci. Tech., Kyushu Univ.).


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