scholarly journals 0.5-V Frequency Dividers in Folded MCML Exploiting Forward Body Bias: Analysis and Comparison

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1383
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Gaetano Palumbo
Keyword(s):  
Power Consumption ◽  
Low Voltage ◽  
Building Blocks ◽  
Frequency Divider ◽  
Cmos Process ◽  
Design Strategies ◽  
Frequency Dividers ◽  
Level Shifter ◽  
Forward Body Bias ◽  
Body Bias

Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at ultra-low voltage thanks to forward body bias are presented, analyzed, and compared. The first considered architecture exploits nType and pType divide-by-two building blocks (DIV2s) without level shifters, whereas the second one is based on the cascade of nType DIV2s with input level shifter. Both the architectures have been previously proposed by the same authors with higher supply voltages, but are able to work at a supply voltage as low as 0.5 V due to the threshold lowering allowed by forward body bias. For each architecture, analytical design strategies to optimize the divider under different operation scenarios are considered and a comparison among all the treated case studies is presented. Simulation results considering a commercial 28 nm FDSOI CMOS process are reported to confirm the advantages and features of the different architectures and design strategies. The analysis show that the use of the forward body bias allows to design frequency dividers which have the best efficiency. Moreover, we have found that the frequency divider architecture based on nType and pType DIV2s without level shifter provides always better performance both in terms of speed and power consumption approaching about 17 GHz of maximum operating frequency with less than 30 μW power consumption.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS

2011 ◽  
Vol 20 (01) ◽  
pp. 125-145 ◽  
Author(s):  
HAILONG JIAO ◽  
VOLKAN KURSUN
Keyword(s):  
Power Consumption ◽  
Distribution Networks ◽  
Cmos Technology ◽  
Sleep Mode ◽  
Design Metrics ◽  
Design Tradeoffs ◽  
Forward Body Bias ◽  
Bouncing Noise ◽  
Circuit Technique ◽  
Body Bias

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

scholarly journals Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

2019 ◽  
Vol 9 (1S5) ◽  
pp. 118-121
Keyword(s):  
Energy Harvesting ◽  
Power Consumption ◽  
Low Voltage ◽  
Threshold Level ◽  
Electronic Systems ◽  
Cmos Inverter ◽  
Switching Speed ◽  
Ultra Low Power ◽  
Level Shifter ◽  
Design Techniques

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to superthreshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms

2016 ◽  
Vol 25 (10) ◽  
pp. 1630006
Author(s):  
Sungkyung Park ◽  
Chester Sungchung Park
Keyword(s):  
Duty Cycle ◽  
High Speed ◽  
Logic Gate ◽  
Memory Systems ◽  
Data Converters ◽  
Frequency Divider ◽  
Cmos Process ◽  
Process Technology ◽  
Dynamic Memory ◽  
Frequency Dividers

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

scholarly journals Design techniques for low-voltage analog integrated circuits

2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Moderate Inversion ◽  
Design Techniques

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

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