scholarly journals Design of Class F Power Amplifier for 2.4ghz using Third Harmonics

2019 ◽  
Vol 8 (3) ◽  
pp. 7370-7375
Keyword(s):  
Power Amplifier ◽  
Large Scale ◽  
High Efficiency ◽  
Supply Voltage ◽  
Travelling Wave ◽  
Input Power ◽  
Engineering Research ◽  
Power Added Efficiency ◽  
Amplification Process ◽  
Class F

Historically, travelling wave tube amplifier (TWTA) has been a common type of Microwave amplifier used commonly in terrestrial and space application due to their high efficiency and power handling capacity. However due to their bulky nature and also being very expensive, it is difficult to use them commercially in a large scale. Inspired by the advantage such as very less development cost, minimum supply voltage, gradual degradation and numerous commercial applications, Solid State Power Amplifier (SSPA) has been the replacement to vacuum tube Technology. The efficiency of the amplifier is one of the most important task in the microwave engineering research. An important figure of merit, power-added efficiency (PAE), is the main focus. Hence in this paper, class F Power amplifier is designed for 2.4GHz frequency. Class F Amplifier is also called as wave shaping amplifier since the harmonics generated helps the amplification process. The class f PA is biased nearer to the class B amplifier (close cut-off area) so the transistor can move back and forth rapidly to produce the harmonics. The efficiency of class F amplifier depends on how many harmonics are used for the amplification process. Here, the amplification process is performed up to the third harmonics which provides 41.606 dBm output power with 27dBm input power. Also a gain of more than 20.277dBm is achieved when the input given is 27dBm. Several other results like reflection Coefficient and transmission coefficient simulations has also been provided with the power added efficiency (PAE) of 75.402 achieved has also been simulated.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

Performance study of an inverse class E power amplifier with series tunable parallel resonant tank

2011 ◽  
Vol 3 (4) ◽  
pp. 405-413 ◽  
Author(s):  
Tao Cao ◽  
Songbai He ◽  
Fei You
Keyword(s):  
Power Amplifier ◽  
Supply Voltage ◽  
Power Gain ◽  
Performance Study ◽  
Power Added Efficiency ◽  
Optimum Operation ◽  
Good Agreement ◽  
Class E ◽  
Class F

An analysis of operation of a modified inverse class E power amplifier is presented. The proposed amplifier that has a series tunable parallel resonant tank is similar to a hybrid of class F and inverse class E. The principles and design equations required to determine the optimum operation of the amplifier are analyzed in detail. The practical circuit using LDMOS MRF21010 is shown to be able to deliver 40.02 dBm outpout power at 155 MHz. The amplifier achieves power-added efficiency (PAE) of 78.18% and drain efficiency of 78.42%, and exhibits 25.02 dB power gain when operates from a 21 V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being achieved.

High-efficiency inverse class-F power amplifier using 3/4 spiral symmetric defected ground structure

2011 ◽  
Vol 3 (6) ◽  
pp. 621-625
Author(s):  
Shilei Jin ◽  
Jianyi Zhou ◽  
Lei Zhang
Keyword(s):  
Power Amplifier ◽  
High Performance ◽  
High Efficiency ◽  
Control Circuit ◽  
Defected Ground Structure ◽  
Ground Structure ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Resonance Frequencies ◽  
Class F

In this article, the development of a high-efficiency power amplifier (PA) with the inverse class-F configuration and a novel 3/4 spiral defected ground structure (DGS) is presented. The proposed DGS structure has improved rejection characteristic and its resonance frequencies are more convenient to adjust than conventional symmetric and asymmetric spiral structure. The electromagnetic-simulated result shows that the proposed circuit has improved harmonic control performance with simplified structure and less return loss than the conventional microstrip harmonic control circuit. The 3/4 spiral harmonics control circuit (HCC) can be modeled by three parallel RLC resonators. Using the proposed structure a high-performance harmonic control circuit is designed for implementing an inverse class-F PA. For comparison, two inverse class-F PAs operating at 2.4 GHz have been implemented by the microstrip HCC and the proposed HCC, respectively. According to the experiment results, the size of the proposed inverse class-F PA is reduced by 20%, the power-added efficiency and the gain are increased by 4.8% and 1.5 dB, respectively.

scholarly journals A 6 GHz Integrated High-Efficiency Class-F−1 Power Amplifier in 65 nm CMOS Achieving 47.8% Peak PAE

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2450
Author(s):  
Syed Muhammad Ammar Ali ◽  
S. M. Rezaul Hasan
Keyword(s):  
Power Amplifier ◽  
Peak Power ◽  
High Efficiency ◽  
Impedance Matching ◽  
Center Frequency ◽  
Dual Purpose ◽  
Power Added Efficiency ◽  
Harmonic Control ◽  
Saturated Output Power ◽  
Class F

This paper reports a “single-transistor” Class-F−1 power amplifier (PA) in 65 nm CMOS, which operates at the microwave center frequency of 6 GHz. The PA is loaded with a Class-F−1 harmonic control network, employing a new “parasitic-aware” topology deduced using a novel iterative algorithm. A dual-purpose output matching network is designed, which not only serves the purpose of output impedance matching, but also reinforces the harmonic control of the Class-F−1 harmonic network. This proposed PA yields a peak power-added efficiency (PAE) of 47.8%, which is one of the highest when compared to previously reported integrated microwave/millimeter-wave PAs in CMOS and SiGe technologies. The amplifier shows a saturated output power of 14.4 dBm along with an overall gain of 13.8 dB.

High-efficiency three-way Doherty power amplifier using reconfigurable PD

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Shiwei Zhao ◽  
Jun Guan ◽  
Xiaoqi Zhou ◽  
Yuehang Xu
Keyword(s):  
Power Amplifier ◽  
Power Distribution ◽  
High Efficiency ◽  
Large Range ◽  
Impedance Matching ◽  
Input Power ◽  
Reverse Voltage ◽  
Power Added Efficiency ◽  
Varactor Diodes ◽  
Doherty Power Amplifier

Abstract In this paper, a new reconfigurable power divider (PD) is proposed to improve the efficiency of the three-way Doherty power amplifier (DPA). The conventional λ/4 transmission line is replaced by the proposed reconfigurable PD in the input of peaking amplifier, where the 90° phase shift and impedance matching can be achieved. Furthermore, the output power distribution ratio (PDR) can be continuously adjusted in a large range by adjusting the reverse voltage of the varactor diodes. Therefore, the reconfigurable PD with the best PDR can assign input power to the peaking amplifier. Experiment results show that the maximum measured power added efficiency (PAE) of the proposed three-way DPA is 49%, which is improved by 5% compared with conventional three-way DPA.

Design of high-efficiency Hybrid Power Amplifier with concurrent F&F−1 class operations for 5G application

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Meisam Tahmasbi ◽  
Farhad Razaghian ◽  
Sobhan Roshani
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
New Method ◽  
Power Added Efficiency ◽  
Hybrid Power ◽  
Novel Structure ◽  
Mode A

Abstract This paper presents a novel structure of Hybrid Power Amplifier (HPA) to operate in two arbitrary classes of operation at two desirable frequencies. The proposed HPA is designed in concurrent F&F−1 classes, simultaneously for 5G application. Presented HPA can solve the harmonics interference problem for concurrent F and F−1 classes and also for any arbitrary class of operation in desired frequencies. The designed HPA operates at 1.5 GHz frequency in the F class mode, while operates at 2.1 GHz frequency in the F−1 class mode. A new method is presented by using two diplexers to provide two paths for signal in different frequencies. Two parallel paths are used at the output of the HPA circuit, so the proposed HPA can operate at two classes. Two diplexers are used in the HPA to make proper isolation between the designed paths. In design of the proposed HPA, according to the utilized diplexers, the amplifier can operate between two arbitrary classes of operation at desired frequencies without any specific switch. The measured drain efficiency (DE) and power added efficiency (PAE) parameters are 57 and 51%, respectively at 2.1 GHz, while measured DE and PAE are 64 and 54%, respectively at 1.5 GHz.

A broadband 23.1 ∼ 27.2 GHz doherty power amplifier with peak output power of 24.3 dBm

Circuit World ◽  
2019 ◽  
Vol 46 (1) ◽  
pp. 1-5
Author(s):  
Yanfeng Fang ◽  
Yijiang Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Input Power ◽  
Content Type ◽  
Fully Integrated ◽  
Power Added Efficiency ◽  
Peak Output Power ◽  
Saturated Output Power ◽  
Direct Input ◽  
Matching Techniques

Purpose This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems. Design/methodology/approach The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation. Findings The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm2 (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply. Originality/value In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
High Efficiency ◽  
Common Source ◽  
Power Performance ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Saturated Output Power

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

Sign in / Sign up

Export Citation Format

Share Document