scholarly journals A 916 nW Power LDO Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

2021 ◽  
Vol 19 ◽  
pp. 311-319
Author(s):  
Hicham Akhamal ◽  
Mostafa Chakir ◽  
Hatim Ameziane ◽  
Mohammed, Akhamal ◽  
Kamal Zared ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
System On Chip ◽  
Drop Out ◽  
Voltage Regulator ◽  
Weak Inversion ◽  
Low Power Dissipation ◽  
On Chip ◽  
Ldo Regulator

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for RadioFrequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The power is 916 nW. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V

scholarly journals Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

2021 ◽  
Vol 15 ◽  
pp. 240-248
Author(s):  
Hicham Akhamal ◽  
Mostafa Chakir ◽  
Hatim Ameziane ◽  
Mohammed Akhamal ◽  
Kamal Zared ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
System On Chip ◽  
Drop Out ◽  
Voltage Regulator ◽  
Weak Inversion ◽  
Low Power Dissipation ◽  
On Chip ◽  
Ldo Regulator

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

scholarly journals An Ultra-Low Power Parity Generator Circuit Based on QCA Technology

2019 ◽  
Vol 2019 ◽  
pp. 1-8 ◽  
Author(s):  
Ismail Gassoumi ◽  
Lamjed Touil ◽  
Bouraoui Ouni ◽  
Abdellatif Mtibaa
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Electrostatic Interactions ◽  
Cmos Technology ◽  
Power Parity ◽  
Ultra Low Power ◽  
Generator Circuit ◽  
Comparison Results ◽  
Low Power Dissipation ◽  
Parity Generator

Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOS technology. It has attracted significant attention in the recent years due to its extremely low power dissipation, high operating frequency, and a small size. In this study, we demonstrate an n-bit parity generator circuit by utilizing QCA technology. Here, a novel XOR gate is used in the synthesis of the proposed circuit. The proposed gate is based on electrostatic interactions between cells to perform the desired function. The comparison results demonstrate that the designed QCA circuits have advantages compared to other circuits in terms of cell count, area, delay, and power consumption. The QCADesigner software, as widely used QCA circuit design and verification, has been used to implement and to verify all of the designs in this study. Power dissipation has been computed for the proposed circuit using accurate QCAPro power estimator tool.

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

2013 ◽  
Vol 321-324 ◽  
pp. 2822-2827 ◽  
Author(s):  
Mao Qiang Duan ◽  
Xiao Li Huang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Hardware Design ◽  
Cmos Technology ◽  
Shift Register ◽  
Vlsi Implementation ◽  
Parallel Method ◽  
Parallel Circuits ◽  
Low Power Dissipation

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

scholarly journals Approximate arithmetic circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 183
Author(s):  
Navabharath Reddy G ◽  
Sruti Setlam ◽  
V. Prakasam ◽  
D. Kiran Kumar
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Integrated Circuit Design ◽  
Compressor Design ◽  
Low Power Dissipation ◽  
Human Sense ◽  
Error Distance

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

scholarly journals A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry

2021 ◽  
Vol 19 ◽  
Author(s):  
Hatim Ameziane ◽  
Kamal Zared ◽  
Hassan Qjidaa
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Weak Inversion ◽  
Fully Depleted ◽  
Op Amp ◽  
Low Power Dissipation ◽  
Adaptive Biasing ◽  
A New Technique

This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC devices in weak inversion. The phase margin is more than 100 degrees for the DC gain of 13.97dB, which is a reasonable margin when temperature range increases.

A Power Supply On-Chip with Low Power Dissipation for Low Power Digital Integrated Circuit Applications

2014 ◽  
Vol 513-517 ◽  
pp. 3844-3849
Author(s):  
Hai Peng Zhang ◽  
Shao Dan Yang ◽  
Ya Dong Yin ◽  
De Jun Wang
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Integrated Circuit ◽  
Power Dissipation ◽  
Cmos Process ◽  
Low Power Dissipation ◽  
Standby Power ◽  
Quiescent Current ◽  
On Chip ◽  
Digital Integrated Circuit

An implementation method of a power supply on-chip (PSOC) was presented for low power digital integrated circuit (IC) applications in this paper. The PSOC consists of a main power supply and a backup low power dissipation power supply, which is featured of micro-standby power consumption and fast switching. The PSOC was designed according to the design rules of SMIC 0.18μm CMOS process and validated both through simulation and silicon verification. The active area is about 0.035mm2 in fact. Post-layout simulation results indicate that output voltage of the PSOC is regulable in the range of 1.52~2.5V as input voltage is in the range of 2.0~3.6V, in which output of the main power supply is regulable in the range of 1.75~ 1.84V. The maximum quiescent current of main power supply is 16.23μA, while the maximum quiescent current of standby power is only 0.552μA. Experimental results indicate that the PSOC is capable of providing energy for the system digital IC implementation. Its power switching time is less than 148μs at the load capacitance of CL =56nF.

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