scholarly journals TI-ADC multi-channel mismatch estimation and calibration in ultra-high-speed optical signal acquisition system

2021 ◽  
Vol 18 (6) ◽  
pp. 9050-9075
Author(s):  
Yongjie Zhao ◽  
◽  
Sida Li ◽  
Zhiping Huang

<abstract> <p>This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.</p> </abstract>

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 73
Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Van-Phu Pham ◽  
Cong-Kha Pham

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.


2019 ◽  
Vol 18 (3-2) ◽  
pp. 17-24 ◽  
Author(s):  
T.Y. Lim ◽  
C. F. Yeong ◽  
E. L. M. Su ◽  
S.M. Shithil ◽  
S.F. Chik ◽  
...  

Map-based navigation is the common navigation method used among the mobile robotic application. The localization plays an important role in the navigation where it estimates the robot position in an environment. Monte Carlo Localization (MCL) is found as the widely used estimation algorithm due to it non-linear characteristic. There are classifications of MCL such as Adaptive MCL (AMCL), Normal Distribution Transform MCL (NDT-MCL) which can perform better than the MCL. However, AMCL is adaptive to particles but the position estimation accuracy is not optimized. NDT-MCL has good position estimation but it requires higher number of particles which results in higher computational effort. The objective of the research is to design and develop a localization algorithm which can achieve better performance in term of position estimation and computational effort. The new MCL algorithm which is named as Adaptive Normal Distribution Transform Monte Carlo Localization (ANDT-MCL) is then designed and developed. It integrates Kullback–Leibler divergence, Normal Distribution Transform and Systematic Resampling into the algorithm. Three experiments are conducted to evaluate the performance of proposed ANDT-MCL in simulated environment. These experiments include evaluating the performance of ANDT-MCL with different path shape, distance and velocity. In the end of the research work, the proposed ANDT-MCL is successfully developed. It is adaptive to the number of particles used, higher position estimation and lower computational effort than existing algorithms. The algorithm can produce better position estimation with less computational effort in any kind paths and is consistent in long journey as well as can outperform in high speed navigation.


Author(s):  
Aleksander Ulyashin ◽  
◽  
Aleksander Velichko ◽  

This paper is devoted to the comparative analysis of modern integrated analog-to-digital converters (ADCs). At the moment, a number of foreign companies, such as Analog Devices, Texas Instruments and Microchip, produce ADCs in integrated design. Each manufacturer uses its own method of implementing the device. The main task of such devices is to convert voltage to binary code. ADCs are used wherever it is necessary to receive an analog signal and process it in digital form. Examples include applications such as communications and telecommunications, various radio systems, and measurement technology. Very important characteristics of such equipment are dynamic range, ease of implementation and speed. The means of analog-to-digital conversion are constantly being improved, which leads to an increase in the speed of the converters and the frequency band of the converted signals, an increase in the dynamic range, sensitivity and accuracy of the ADC. Significant interest in high-speed ADCs with a large dynamic range is explained by the fact that in the vast majority of telecommunications and radio engineering systems, direct signal conversion schemes without intermediate frequency conversion are increasingly used. Broadband applications have also been developed. The main requirement in these applications is the high sensitivity and wide dynamic range of the transducer for simultaneous detection of strong and weak signals. In this paper, a comparative analysis of the main types of analog-to-digital converters offered on the market is carried out in order to identify the most optimal construction method for using it in modern equipment.


2018 ◽  
Author(s):  
Ranajay Mandal ◽  
Nishant Babaria ◽  
Jiayue Cao ◽  
Zhongming Liu ◽  

AbstractStrong electromagnetic fields that occur during functional magnetic resonance imaging (fMRI) presents a challenging environment for concurrent electrophysiological recordings. Here, we present a miniaturized, wireless platform – “MR-Link” (Multimodal Recording Link) that provides a hardware solution for simultaneous electrophysiological and fMRI signal acquisition. The device detects the changes in the electromagnetic field during fMRI to synchronize amplification and sampling of electrophysiological signals with minimal artifacts. It wirelessly transmits the recorded data at a frequency detectable by the MR-receiver coil. The transmitted data is readily separable from MRI in the frequency domain. To demonstrate its efficacy, we used this device to record electrocardiograms and somatosensory evoked potential during concurrent fMRI scans. The device minimized the fMRI-induced artifacts in electrophysiological data and wirelessly transmitted the data back to the receiver coil without compromising fMRI signal quality. The device is compact (22 mm dia., 2gms) and can be placed within the MR-bore to precisely synchronize with fMRI. Therefore, MR-Link offers an inexpensive system by eliminating the need for amplifiers with a high dynamic range, high-speed sampling, additional storage or synchronization hardware for electrophysiological signal acquisition. It is expected to enable a broader range of applications of simultaneous fMRI and electrophysiology in animals and humans.


2013 ◽  
Vol 655-657 ◽  
pp. 978-983
Author(s):  
Hui Yong Sun ◽  
Peng Cao

The Time-Interleaved ADC(TIADC) is an effective method for implement ultra high-speed data acquisition. However, the errors of channel mismatch are seriously degrade the signal-to-noise ratio of the system, such as Time-skew error, Gain error and Offset error. This paper have done some researches and analysis, and given the modeling of the three channels mismatch. What's more, it also given a detailed analysis of error and the method of measure it, derived the formula of signal to noise and distortion ratio(SINAD) and spurious free dynamic range(SFDR). All of them provide a reference for the tolerance range of TIADC channel mismatch error. Meanwhile, the result of this paper has provided a theoretical basis for eliminating TIADC channel mismatch error.


2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.


Sign in / Sign up

Export Citation Format

Share Document