A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture

2012 ◽  
Vol 263-266 ◽  
pp. 9-14 ◽  
Author(s):  
Hong Gang Zhou ◽  
Qiang Song ◽  
Chun Yu Peng ◽  
Shou Biao Tan
Keyword(s):  
Great Improvement ◽  
Error Rate ◽  
Cmos Technology ◽  
Soft Error ◽  
Dynamic Power ◽  
Soft Error Rate ◽  
Sram Cell ◽  
Simulation Results ◽  
The Cross

A new 10T SRAM cell is proposed in this paper for simultaneously addressing the half select problem and improving the read/write stability. Without the half select condition, the proposed 10T cell allows efficient bit-interleaving to provide soft error rate protection and the dynamic power is also decreased significantly due to the reduction in the number of bitlines discharged and charged during the read and write operation. In the new 10T SRAM cell, one side of the cross-coupled inverters cuts off the pull up path or pull down path through adding two gated transistors according to the write ‘0’ or ‘1’ operation. It brings a great improvement for write stability without considering the half select disturb during the write operation. The simulation results indicate that the RSNM and WM of the proposed SRAM cell are enhanced by 130% and 58%, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology.

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

Statistical soft error rate estimation of combinational circuits using Bayesian networks

2016 ◽  
Vol 35 (5) ◽  
pp. 1760-1773
Author(s):  
M. Amin Sabet ◽  
Behnam Ghavami
Keyword(s):  
Bayesian Networks ◽  
Error Rate ◽  
Process Variation ◽  
Joint Probability ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Soft Error ◽  
Combinational Circuits ◽  
Content Type ◽  
Soft Error Rate

Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

Experimental Soft Error Rate of Several Flip-Flop Designs Representative of Production Chip in 32 nm CMOS Technology

2013 ◽  
Vol 60 (6) ◽  
pp. 4226-4231 ◽  
Author(s):  
Gilles Gasiot ◽  
Maximilien Glorieux ◽  
Sylvain Clerc ◽  
Dimitri Soussan ◽  
Fady Abouzeid ◽  
...  
Keyword(s):  
Error Rate ◽  
Cmos Technology ◽  
Soft Error ◽  
Flip Flop ◽  
Soft Error Rate
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