The Effect of Alkaline Slurry on Low-K Film

2011 ◽  
Vol 295-297 ◽  
pp. 1621-1624
Author(s):  
Yi Hu ◽  
Yu Ling Liu ◽  
Li Ran Wang ◽  
Xiao Yan Liu ◽  
Yan Gang He
Keyword(s):  
Dielectric Properties ◽  
Time Delay ◽  
Integrated Circuits ◽  
Process Integration ◽  
Process Conditions ◽  
Static Test ◽  
Low Dielectric ◽  
Chemical Mechanical Polishing Process ◽  
The Impact ◽  
Low K

As the integrated circuits developing, the line-width and space between the metal interconnection are shrinking. This increases the RC time delay. To reduce the RC time delay, the low dielectric constant (low-k) material was introduced in the ICs. For process integration considerations, the impact of electronic characters was investigated. In this paper, both static test and CMP(chemical mechanical polishing) process conditions were executed on the low-kmaterial black diamond (BD) with slurry,which was explored by Hebei University of Technology. The slurry was utilized to evaluate the effect on the dielectric properties of BD films. Electrical analyses have shown dielectric properties of BD films would not be degraded during these processes. The static test was dipping the low–k material (BD)in the slurry for 30s and 2minutes, and the results showed the capacitance changed from 3.01to3.40 when dipping in 30s ,and the value reached 3.71 when dipping 2minutes. The resistance changed from 2.9-2.95 to 3.27-3.33 in 30s,and reached 3.57-3.63 in 2 minutes. The result of CMP process showed that the capacitance of five dots , which were selected on the BD film, changed from 2.94-2.98to 2.99-3.05. The dielectric integrity of lowkBD films after CMP process remained at an acceptable region to meet requires of multilevelinterconnection.

Process Integration issues for Interlevel Dielectric Materials for Sub-quarter Micron Silicon Integrated Circuits

1998 ◽  
Vol 511 ◽  
Author(s):  
Vijay Parihar ◽  
R. Singh
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Process Integration ◽  
Dielectric Materials ◽  
New Approach ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Silicon Integrated Circuits ◽  
Processing Techniques ◽  
Low K

ABSTRACTThe continued miniaturization towards sub-quarter micron feature size mandates the search for low dielectric constant interlayer dielectric materials. A large number of materials and processing techniques has been suggested, but so far none of the proposed dielectric materials as well as processing techniques have been integrated into standard integrated circuit processing. In this paper, a new approach has been formulated for integration of low-k dielectric materials for future integrated circuits.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Delamination analysis of Cu/low-k technology subjected to chemical-mechanical polishing process conditions

2006 ◽  
Vol 46 (9-11) ◽  
pp. 1679-1684 ◽  
Author(s):  
C. Yuan ◽  
W.D. van Driel ◽  
R. van Silfhout ◽  
O. van der Sluis ◽  
R.A.B. Engelen ◽  
...  
Keyword(s):  
Chemical Mechanical Polishing ◽  
Mechanical Polishing ◽  
Process Conditions ◽  
Polishing Process ◽  
Chemical Mechanical Polishing Process ◽  
Low K

Novel Materials as Interlayer Low-K Dielectrics for CMOS Interconnect Applications

2011 ◽  
Vol 110-116 ◽  
pp. 5380-5383
Author(s):  
Tejas R. Naik ◽  
Veena R. Naik ◽  
Nisha P. Sarwade
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuits ◽  
Dielectric Materials ◽  
Low Dielectric Constant ◽  
Interlayer Dielectric ◽  
Novel Materials ◽  
Low Dielectric ◽  
Processing Properties ◽  
New Generation ◽  
Low K

Scaling down the integrated circuits has resulted in the arousal of number of problems like interaction between interconnect, crosstalk, time delay etc. These problems can be overcome by new designs and by use of corresponding novel materials, which may be a solution to these problems. In the present paper we try to put forward very recent development in the use of novel materials as interlayer dielectrics (ILDs) having low dielectric constant (k) for CMOS interconnects. The materials presented here are porous and hybrid organo-inorganic new generation interlayer dielectric materials possessing low dielectric constant and better processing properties.

Rapid Thermal Processing of Hydrogen Silsesquioxane for Low Dielectric Constant Performance

1999 ◽  
Vol 565 ◽  
Author(s):  
J. N. Bremmer ◽  
D. Gray ◽  
Y. Liu ◽  
K. Gruszynski ◽  
S. Marcus
Keyword(s):  
Dielectric Constant ◽  
Thermal Processing ◽  
Low Dielectric Constant ◽  
Process Conditions ◽  
Low Density ◽  
Hydrogen Silsesquioxane ◽  
Thermal Cure ◽  
Cure Process ◽  
Low Dielectric ◽  
Low K

AbstractLow dielectric constant hydrogen silsesquioxane films were achieved by rapid thermal cure processing with production viable equipment. A reduced dielectric constant of k = 2.5–2.6 is demonstrated by optimizing rapid thermal cure process conditions to produce low density hydrogen silsesquioxane thin films. This is a significant reduction relative to production proven furnace cure processed hydrogen silsesquioxane with k = 2.9. Concurrent with reduced k performance is a characteristic film expansion which contributes to formation of a low density structure. A mechanism for film expansion and relevance to low k performance is described; and issues relative to integration of rapid thermal processed low k hydrogen silsesquioxane are discussed.

Impact of CMP Polish and pCMP Cleaning on Adhesion of SiCN Capping Layer on PECVD-Derived Porous OSG and Copper

2009 ◽  
Vol 145-146 ◽  
pp. 377-380
Author(s):  
Dave M. Gage ◽  
A.D.W. Thiel ◽  
R.H. Dauskardt ◽  
M.K. Haas ◽  
L.M. Matz ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Dielectric Material ◽  
Process Conditions ◽  
Copper Films ◽  
Cleaning Process ◽  
Pore Former ◽  
Low Dielectric ◽  
Low Dielectric Constant Materials ◽  
The Impact ◽  
Robust Integration

The development of robust integration processes for low-dielectric-constant materials is critical in order to meet the ITRS timeline. For 45 nm and beyond, the roadmap dictates use of an advanced dielectric material with a bulk dielectric constant below 2.5. These materials are produced through the introduction of nanometer-scale porosity into an OSG skeleton. The pore size, morphology, and interconnectivity is controlled by the choice of OSG precursor, pore former, and process conditions. During integration, liquids can be absorbed into the pore network (e.g. during the polishing and cleaning process steps, resulting in a degradation of the electrical and mechanical properties [1-3]. The objective of this paper is to evaluate the impact of the CMP and post-CMP cleaning process steps on cohesive fracture in a porous OSG dielectric and the adhesive fracture of SiCN cap with porous OSG and copper films.

Some Aspects of the Materials Science of Low-K Integration

2003 ◽  
Vol 766 ◽  
Author(s):  
Vincent McGahay
Keyword(s):  
Dielectric Constant ◽  
Integrated Circuits ◽  
Materials Science ◽  
Low Dielectric Constant ◽  
Basic Principles ◽  
Materials Properties ◽  
Low Dielectric ◽  
Critical Insight ◽  
Low K ◽  
Insight Into

AbstractThe microelectronic industry's transition to low dielectric constant insulators in the wiring levels of integrated circuits has proven to be more difficult than expected. Materials properties are an integral part of the problem, as much for yield as for reliability. Unfortunately, many properties which are important for manufacturing robustness tend to degrade as the dielectric constant is lowered. Although materials properties are a useful guide to low-K manufacturability, inflexibility with regard to specifications could ultimately limit future progress. Application of basic principles of materials science to the integration of low-K dielectrics can give critical insight into the nature of the difficulties. Several examples of problems in low-K integration which benefit from such analysis are given.

An effective strategy for the preparation of intrinsic low-k and ultralow-loss dielectric polysiloxanes at high frequency by introducing trifluoromethyl groups into the polymers

2020 ◽  
Vol 11 (38) ◽  
pp. 6163-6170
Author(s):  
Fengping Liu ◽  
Xingrong Chen ◽  
Linxuan Fang ◽  
Jing Sun ◽  
Qiang Fang
Keyword(s):  
Dielectric Constant ◽  
Dielectric Properties ◽  
Dielectric Loss ◽  
High Frequency ◽  
Low Dielectric Constant ◽  
Effective Strategy ◽  
Low Dielectric ◽  
5 Ghz ◽  
Low K ◽  
Trifluoromethyl Groups

Two new CF3-containing polysiloxanes with low dielectric constant (Dk) and dielectric loss (Df ) at a high frequency of 5 GHz were reported. The sample with two −CF3 groups exhibits better dielectric properties with Dk of 2.53 and ultralow Df of 1.66 × 10−3.

Integration Issues for Low Dielectric Constant Materials in each Generation of ULSI'S

1999 ◽  
Vol 565 ◽  
Author(s):  
Hideki Gomi ◽  
Koji Kishimoto ◽  
Tatsuya Usami ◽  
Ken-ichi Koyanagi ◽  
Takashi Yokoyama ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Silicon Oxide ◽  
Process Integration ◽  
Low Dielectric Constant ◽  
Next Generation ◽  
Hydrogen Silsesquioxane ◽  
Low Dielectric ◽  
Low Dielectric Constant Materials ◽  
Fluorinated Silicon Oxide ◽  
Low K

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-μm and 0.18-μm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.

Integration Issues for Low Dielectric Constant Materials in each Generation of ULSI's

1999 ◽  
Vol 564 ◽  
Author(s):  
Hideki Gomi ◽  
Koji Kishimoto ◽  
Tatsuya Usami ◽  
Ken-ichi Koyanagi ◽  
Takashi Yokoyama ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Silicon Oxide ◽  
Process Integration ◽  
Low Dielectric Constant ◽  
Next Generation ◽  
Hydrogen Silsesquioxane ◽  
Low Dielectric ◽  
Low Dielectric Constant Materials ◽  
Fluorinated Silicon Oxide ◽  
Low K

AbstractThe technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-µm and 0.1 8-µm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.

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