Design of FPGA-Based Fault-Tolerant Embedded System

2012 ◽  
Vol 546-547 ◽  
pp. 1574-1579
Author(s):  
Zhi Wen Xiong ◽  
Wen Feng Wang ◽  
Hong Zeng
Keyword(s):  
Fault Tolerance ◽  
Embedded Systems ◽  
Embedded System ◽  
Fault Tolerant ◽  
Design Method ◽  
Data Acquisition System ◽  
Fault Tolerant System ◽  
System Developer ◽  
Hardware Faults ◽  
Adaptive Ability

Fault tolerant is one of major requirements for embedded systems. As the embedded systems become more and more complex, more chances for various fault. When design embedded system developer has to handle these faults. Before handling faults designer has to identify and understand the types and nature of faults.Faults is the sources for low dependability, faults can be hardware and software. Hardware faults can be distinguished from systematic faults like software or design errors. The Fault can be deleted, such as extensive testing or formal verification and tolerated by fault tolerance techniques. We restrict ourselves to the problem of fault tolerance and refer to other methods for troubleshooting.This paper discusses a new design method about the fault tolerant system of embedded system. We designed a fault tolerant system of data acquisition system in dynamically re-configurable FPGA. The experiment results show that the system not only be able to higher self-adaptive ability and reliability, but also can Through the FGPA to complete a specific algorithm.

scholarly journals An Efficient Fault-Tolerant Multi-Bus Data Scheduling Algorithm Based on Replication and Deallocation

2016 ◽  
Vol 16 (2) ◽  
pp. 69-84
Author(s):  
Chafik Arar ◽  
Mohamed Salah Khireddine
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Fault Tolerant ◽  
Scheduling Algorithm ◽  
Experimental Results ◽  
Data Scheduling ◽  
Heterogeneous Architectures ◽  
Hardware Faults

Abstract The paper proposes a new reliable fault-tolerant scheduling algorithm for real-time embedded systems. The proposed scheduling algorithm takes into consideration only one bus fault in multi-bus heterogeneous architectures, caused by hardware faults and compensated by software redundancy solutions. The proposed algorithm is based on both active and passive backup copies, to minimize the scheduling length of data on buses. In the experiments, this paper evaluates the proposed methods in terms of data scheduling length for a set of DAG benchmarks. The experimental results show the effectiveness of our technique.

Genetic multistart algorithm for the design of fault-tolerant systems

2008 ◽  
Vol 222 (1) ◽  
pp. 17-29
Author(s):  
K Echtle ◽  
I Eusgeld ◽  
D Hirsch
Keyword(s):  
Genetic Algorithm ◽  
Fault Tolerance ◽  
Fault Tolerant ◽  
Design Method ◽  
Fitness Function ◽  
Evolutionary Process ◽  
Mechatronic Systems ◽  
Fast Evaluation ◽  
Pareto Solution ◽  
Fault Tolerant Systems

This paper presents a new approach to the multiobjective design of fault-tolerant systems. The design objectives are fault tolerance and cost. Reducing the cost is of particular importance for fault-tolerant systems because the overhead caused by redundant components is considerable. The new design method consists of a special genetic algorithm that is tailored to the particular issues of fault-tolerant systems. The interface of the present tool ePADuGA (elitist and Pareto-based Approach to Design fault-tolerant systems using a Genetic Algorithm) allows for adaptation to various fields of application. The degree of fault tolerance is measured by the number of tolerated faults rather than traditional reliability metrics, because reliability numbers are mostly unknown during early design phases. The special features of the genetic algorithm comprise a graph-oriented representation of systems (which are the individuals during the evolutionary process), a simple yet expressive fault model, a very efficient procedure for fault-tolerance evaluation, and a Pareto-oriented fitness function. In a genetic algorithm generating thousands of individuals, a very fast evaluation of each individual is mandatory. For this purpose, state-space-oriented evaluation methods have been cut down to an extremely simple function which is still sufficient to assess the fault tolerance of individuals. An innovative aspect is also a multistart technique to find a Pareto solution set, which is independent of any parameters. In this paper, experimental results are presented showing the feasibility of the approach as well as the usefulness of the final fault-tolerant architectures, particularly in the field of mechatronic systems.

Design of an Intelligent Fault-Tolerant System for Real-World Applications

1994 ◽  
Vol 6 (2) ◽  
pp. 150-154
Author(s):  
Shigeki Abe ◽  
◽  
Michitaka Kameyama ◽  
Tatsuo Higuchi ◽  
◽  
...  
Keyword(s):  
Real World ◽  
Error Detection ◽  
Fault Tolerant ◽  
Point Of View ◽  
Fault Tolerant System ◽  
Knowledge Based ◽  
Real World Applications ◽  
Hardware Faults ◽  
Modular Redundancy ◽  
Inference Strategy

To achieve the safety of an intelligent digital system for real-world applications, not only the hardware faults in the processors but also any other faults and errors related to the real world such as sensor faults, actuator faults and human errors must be removed. From this point of view, an intelligent fault-tolerant system for real-world applications is proposed based on triple-modular redundancy. The system consists of a master processor that performs the actual control operations and two redundant processors which simulate real-world process together with the control operations using knowledge-based inference strategy. To realize the independency between the triplicated modules, the simulation for error detection and recovery is performed without actual external sensor signals used in the master processor.

Wireless Order-Meal System Design Based on QT and ARM

2012 ◽  
Vol 426 ◽  
pp. 400-403 ◽  
Author(s):  
Guang Nan Zhang
Keyword(s):  
Wireless Communication ◽  
Embedded Systems ◽  
Embedded System ◽  
System Design ◽  
Communication Technology ◽  
Design Method ◽  
Embedded Technology ◽  
Server System

A kind of design method of a complete Wireless Order-Meal System based on embedded systems and wireless communication technology is propsoed. Making use of the S3C2410, PXA270 and linux2.6 to build embedded system platform;selecting wireless WI-FI techniques to realize the wireless communication between subsystems; using Qt/embedded technology to develop the interface of embedded system; developing server system of backstage management using the JSP + MySQL5.0.

scholarly journals Design of a Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter

2019 ◽  
Vol 8 (9) ◽  
pp. 2647-2651
Keyword(s):  
Fault Tolerance ◽  
High Performance ◽  
Fault Tolerant ◽  
Digital Signal ◽  
Fir Filter ◽  
Delay Reduction ◽  
Flip Flop ◽  
Multiple Faults ◽  
Fault Tolerant System ◽  
Logic Unit

Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.

scholarly journals A Fault Tolerant Scheduling Heuristics for Distributed Real Time Embedded Systems

2018 ◽  
Vol 18 (3) ◽  
pp. 48-61 ◽  
Author(s):  
Bachir Malika ◽  
Hamoudi Kalla
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Task Scheduling ◽  
Fault Tolerant ◽  
Scheduling Algorithms ◽  
Task Graphs ◽  
Heterogeneous Processing ◽  
Mapping Task ◽  
Hardware Faults ◽  
Independent Tasks

Abstract In this paper, fault tolerant task scheduling algorithms are proposed for mapping task graphs to heterogeneous processing nodes. These scheduling heuristics that we propose are redundancy-based software to tolerate hardware faults. We consider only processor permanent failures with a fail-silent behavior. The proposed heuristics generate automatically a real-time fault distributed schedule of dependent and independent tasks into heterogonous multiprocessors architecture. The heuristics are based on active and passive redundancy.

scholarly journals A Software Architecture for Handling Complex Critical Section Constraints on Multiprocessors in a Fault-Tolerant Real-Time Embedded System

10.29007/brkj ◽  
2019 ◽  
Author(s):  
Jia Xu
Keyword(s):  
Fault Tolerance ◽  
Embedded System ◽  
Software Architecture ◽  
Real Time ◽  
Data Structures ◽  
Fault Tolerant ◽  
Critical Section ◽  
Shared Data ◽  
Time Task ◽  
Critical Sections

In a real-time embedded system which uses a primary and an alternate for each real-time task to achieve fault tolerance, there is a need to allow both primaries and alternates to have critical sections/segments in which shared data structures can be read and updated while guaranteeing that the execution of any part of one critical section will not be interleaved with or overlap with the execution of any part of a critical section belonging to some other primary or alternate which reads and writes on those shared data structures. In this paper a software architecture is presented which effectively handles critical section constraints where both primaries and alternates may have critical sections which can either overrun or underrun, while still guaranteeing that all primaries or alternates that do not overrun will always meet their deadlines while keeping the shared data in a consistent state on a multiprocessor in a fault tolerant real-time embedded system.

scholarly journals Building Fault Tollrence within Clouds at Network Level

2016 ◽  
Vol 6 (4) ◽  
pp. 1560
Author(s):  
Sastry Kodanda Rama Jammalamadaka ◽  
Kamesh Bala Krishna Duvvuri ◽  
Devi Anusha CH ◽  
Padmini P ◽  
Siva Anjaneyulu G
Keyword(s):  
Cloud Computing ◽  
Fault Tolerance ◽  
Network Design ◽  
Fault Tolerant ◽  
Design Method ◽  
Cost Effective ◽  
High Availability ◽  
Computing Technologies ◽  
Network Software

<span>Cloud computing technologies and infrastructure facilities are coming up in a big way making it cost effective for the users to implement their IT based solutions to run business in most cost-effective and economical way. Many intricate issues however, have cropped-up which must be addressed to be able to use clouds the purpose for which they are designed and implemented. Among all, fault tolerance and securing the data stored on the clouds takes most of the importance. Continuous availability of the services is dependent on many factors. Faults bound to happen within a network, software, and platform or within the infrastructure which are all used for establishing the cloud. The network that connects various servers, devices, peripherals etc., have to be fault tolerant to start-with so that intended and un-interrupted services to the user can be made available. A novel network design method that leads to achieve high availability of the network and thereby the cloud itself has been presented in this paper</span>

scholarly journals Técnicas de Tolerância a Falhas em uma Plataforma para Prototipagem Rápida Usando Microcontroladores

2019 ◽  
Author(s):  
Kleber Kruger ◽  
Fabio Iaione
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Rapid Prototyping ◽  
System Performance ◽  
Processing Time ◽  
Fault Tolerant ◽  
Weather Station ◽  
Fault Tolerant System ◽  
Sram Memory

This paper describes the implementation of fault tolerance techniques (based on data and processing redundancy) in programming of a rapid prototyping platform using microcontrollers. To evaluate performance of these techniques was used a fault injector software and a weather station system as a case study. Experiments simulated faults in sensor readings and faults in SRAM memory regions of the weather station. Finally, the fault-tolerant system performance is presented in comparison with non-fault-tolerant system, considering incidence of failures, processing time, memory and power consumption.

Building Fault Tollrence within Clouds at Network Level

2016 ◽  
Vol 6 (4) ◽  
pp. 1560
Author(s):  
Sastry Kodanda Rama Jammalamadaka ◽  
Kamesh Bala Krishna Duvvuri ◽  
Devi Anusha CH ◽  
Padmini P ◽  
Siva Anjaneyulu G
Keyword(s):  
Cloud Computing ◽  
Fault Tolerance ◽  
Network Design ◽  
Fault Tolerant ◽  
Design Method ◽  
Cost Effective ◽  
High Availability ◽  
Computing Technologies ◽  
Network Software

<span>Cloud computing technologies and infrastructure facilities are coming up in a big way making it cost effective for the users to implement their IT based solutions to run business in most cost-effective and economical way. Many intricate issues however, have cropped-up which must be addressed to be able to use clouds the purpose for which they are designed and implemented. Among all, fault tolerance and securing the data stored on the clouds takes most of the importance. Continuous availability of the services is dependent on many factors. Faults bound to happen within a network, software, and platform or within the infrastructure which are all used for establishing the cloud. The network that connects various servers, devices, peripherals etc., have to be fault tolerant to start-with so that intended and un-interrupted services to the user can be made available. A novel network design method that leads to achieve high availability of the network and thereby the cloud itself has been presented in this paper</span>

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